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In an earlier blog, we had talked about design for manufacturability (DFM) and discussed how the DesignTrue DFM feature of Allegro® PCB Editor provides a cost-effective and timely solution to proactively work towards reducing manufacturing issues, both assembly-related (DFA) and fabrication-related (DFF), in the design phase itself. In that post, I had promised to talk more about DesignTrue DFM. So, here we go with the mask-defined pin annular ring checks.
Whether to go the solder mask-defined (SMD) way or the metal-defined (non-mask defined or NSMD) way for your padstacks is usually determined to a great extent by the datasheets of the parts you are using. But sometimes, you will make that decision yourself too. Although it boils down, in the most simplistic language possible, to whether you want the solder mask to be smaller than the pin pad (SMD) or you want the solder mask to be bigger than the pin pad (NSMD), the ramifications are not that simple and is, in addition to the practical issues, a point of huge debate. We will of course not venture into the finer points of this debate but assume that for whatever reasons, we have mask-defined pins in our design, maybe because we want to prevent an outflow of solder by containing the solder ball of a BGA within the pin pad. And, we want our design to be fabricated correctly and as intended.
So what do we have here? Simply put a mask, a pad, and an annular ring. To be even more specific we want the mask opening to be what we specify. We want the mask size to be smaller than the pin but by only so much. So, we want a way to measure the annular ring of the mask inside the pin pad.
We just stated the problem, which also defines our needs. Now, for the good news. PCB Editor has exactly what we need - annular ring checks that can be applied to SMD pins. And it's an easy three-step process.
Before starting with the steps, set up the visibility of the mask layers and pins using the Color dialog. And as an aside, I used SMD as "solder mask-defined" and not as "surface mount device", which a totally different story for another time, maybe.
That's quite simple - set Pad to mask under Mask defined pad in the Analysis Modes window (Setup – Constraints – Modes).
This will flag a DRC if the distance between mask and pad is more than the specified constraints that we will set in the next step.
We will set up constraints in Constraint Manager (Setup – Constraints – Constraint Manager). Simply create a DFFAnnularRingCSet of non-etch type and then define the Mask spacing and Mask defined pad values.
You either have mask layers defined in your stack up or not. If mask layers are defined, they will be loaded in the Design – Annular Ring category under Design for Fabrication in Constraint Manager. Simply assign the CSet created in Step #2 to the mask layers.
If mask layers are not defined, use the Add Subclass Group popup option to add mask layers and assign the CSet.
The only thing left now is to set Mask_Defined_Pin_Type for the pin to True in Edit Property (Edit – Properties).
And, you are done with applying annular ring fabrication spacing constraint for mask defined pins!
Of course, you will want to see the DRCs, if any. But that's easy. Choose Tools – Update DRC to update the new constraint set (CSet) you just created and then choose Display – Status – DRC to view the DRCs. If you then want to debug the values, use the Padstack Editor window or the DRC Browser window.
If you want to try out the steps and explore different ways of setting up spacing constraints between the mask layers to the copper pads (annular ring spacing) and determine the DRC violations, I recommend the Design For Fabrication (DFF) – Mask Defined Pin Annular Ring Checks Application Note at Cadence Online Support. This Application Note goes into details of each of the steps listed in this post and has information on troubleshooting.