Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take sneak preview of recently published documents. You can access the database by logging onto https://support.cadence.com/.

Rapid Adoption Kits (RAK)

Allegro PCB Librarian XL Tutorial
This tutorial will guide users through a tour of developing library data utilizing PCB Librarian XL. You will review symbol development and the associated informational views as well as Allegro footprints as part of this material.

Constraint Manager Net Class-Class Constraint Set Assignment Matrix
This RAK demonstrates the process for establishing spacing rules between net classes using the new CSet assignment matrix in Constraint Manager.

SiP Layout Auto Connect
This RAK is intended to provide instruction on the advantage of SiP Layout Auto Connect. The intent of the auto connect feature is to reduce design cycle time for both feasibility studies and product designs by reducing the time it takes to hand draw traces (clines or connect lines) of the logical interconnect.

Application Notes

Allegro Design Workbench: Optimized Library Flow Tutorial
The default library flow in ADW is divided into different Model types. Then, there is a New and ECO sub flow for each model type. There is a great deal of overlap in the New and ECO Flow. This document discusses a New Library Flow called the Optimized Library Flow. It combines these two sub flows into a single flow. It also adds some additional capability to allow you to easily import models created by third party vendors. This tutorial will highlight the changes in the flow and several library related tasks.

Allegro Design Workbench : Part Validation
One of ADW Library Workbench's function is to automatically run a check between the Part Number, the Schematic Symbol and Footprint to verify that the Symbol and the Footprint are compatible. This will be referred to as the Front-To-Back check (FTB), and the utility is con2con.exe. This validation can only happen when there is a Part Number linked to (associated with) a Schematic Symbol and a Footprint. When con2con runs, it performs all the checks in memory, which means that a Schematic and Allegro Board file are never output.

How to Create Laminate RF Symbols from GDS Data
This Application Note describes a process for creating Laminate RF symbols from GDS files using SiP Layout.

Videos

Creating Fillets for BGA Package Configuration
This video explains what a fillet is and it's importance. Video then shows steps to create fillets.

Troubleshooting articles

You can access recently published troubleshooting articles by clicking Here.

Training Bytes:

Self-learning videos to learn more on the tools can be seen from Training Bytes. New videos have been published for:

• Allegro Design Entry HDL
• Allegro PCB Editor
• Sigrity Power and Signal Integrity

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Hope you find these knowledge resources useful.

Jasmine