Cadence Sigrity SystemSI Technology Highlighted at CDNLive SV 2016

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations from 12 different technical tracks. More than 25 exhibitors participated in the Designer Expo.

The IC Packaging/Signal Integrity/Power Integrity track featured customer papers on co-design as well as signal, power, and thermal integrity. With the challenge of creating final products as quickly and as efficiently as possible, two papers stood out as audience favorites. It is no surprise that each of these papers utilized a number of Sigrity™ tools in the methodology, but ultimately utilized Sigrity SystemSI™ technology to ensure the product was working to industry compliance standards.

The first user paper highlighting SystemSI technology was presented by Ken Wu of Google. Ken showed the audience one of the latest Google Chromebooks and discussed the challenge of USB Type-C connectors and the multi-gigabit USB SuperSpeed interface design. Ken walked through both pre-layout analysis and post-route analysis and using Sigrity technology to check compliance of the interface.

To review and download Ken Wu’s paper, click the image below.

Another user paper highlighting use of Sigrity technology was delivered by Alex Tain of Seagate. He discussed methodologies used in creating Seagate solutions utilizing Flash technology.

Alex reviewed his design and analysis methodology, which includes using Allegro implementation tools for the PCB and IC package design. The methodology also utilizes Sigrity tools for analysis, interconnect extraction, and interface compliance testing.

To see Alex’s paper and how Seagate performs Flash memory interface simulations, click on the image below.

Thanks to Ken Wu, Alex Tain, and all the other contributors to CDNLive SV 2016. It was a lively and highly educational conference.

Team Allegro