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A new year means another DesignCon and 2010 is an exciting year for the PCB and IC Packaging team at Cadence – sometimes known as TeamAllegro.This year you will find the Cadence booth at an ideal location in the center of the Exhibition floor. We will have a demo pod dedicated to Allegro and SiP. We’ll be happy to show you the latest technology around multi-gigabit, DDR3, and power integrity as it works seamlessly with Allegro PCB, IC Packaging, and Cadence SiP design databases.We are also very proud to be demonstrating the new user interface for our Signal Integrity tool.
This new version can utilize IBIS models directly as well HSpice and Spectre transistor models through a simple import wizard.
One other feature you should drop by and see is the new multi-gigabit screening feature that guides you to the routed signals on your board that are most likely to give you trouble with compliance testing.