Come See TeamAllegro at DesignCon2010

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC Packaging team at Cadence – sometimes known as TeamAllegro.

This year you will find the Cadence booth at an ideal location in the center of the Exhibition floor.  We will have a demo pod dedicated to Allegro and SiP.  We’ll be happy to show you the latest technology around multi-gigabit, DDR3, and power integrity as it works seamlessly with Allegro PCB, IC Packaging, and Cadence SiP design databases.

We are also very proud to be demonstrating the new user interface for our Signal Integrity tool.

This new version can utilize IBIS models directly as well HSpice and Spectre transistor models through a simple import wizard.

 

One other feature you should drop by and see is the new multi-gigabit screening feature that guides you to the routed signals on your board that are most likely to give you trouble with compliance testing.

This year, we will be taking special note of the paper being delivered by Donald Telian and Sergio Camerllo as they discuss simulation and modeling techniques for 6+ Gbps channel design.  Use this link to get this session added to your calendar.

One other thing to note is that social media will have a big role at this year’s DesignCon.  Cadence will be participating in a panel on social media that we hope you will attend.  Those of you on Twitter should be following @DesignCon2010 and you may also want to follow @TeamAllegro.  We will keep you posted on activities throughout the event.

Let us know your thoughts on DesignCon2010 as well as the latest features in Allegro and SiP.

Brad Griffin