PCB Design Blogs

Today we take a break from our regular posts on Allegro System Capture features and basics to announce a Cadence Training webinar on System-Level Design with Senior Application Engineer, Dave Palumbo.  

What Is this Webinar About?

In the product design world, there is a disconnect between system architecture design and implementation. Creating a system that meets cost, performance, and form factor requirements is a constant challenge for design architects and hardware designers. There is a need for products that can help them design systems to meet the goals of their end products within the time-to-launch window.

This brings us to a different facet of Allegro System Capture. In addition to being a powerful schematic capture application and a comprehensive design environment, Allegro System Capture is also a scalable, easy-to-use solution for quick system design intent creation.

Using the system-level design features of Allegro System Capture, you can create high-level system architecture and functional block diagrams that stay connected to the detailed implementation of each board in the product. You have an intuitive, easy-to-use environment for designing systems that are correct by construction.

Moreover, a system can be partitioned into multiple boards to ensure that system assembly and connectivity are current from the beginning and throughout the design process. Allegro System Capture also enables the high-level functional and architectural description of the multi-board system to stay in sync with the detailed implementation of each of the boards in the system.

 What Will the Webinar Cover?

 The Cadence Training team brings to you an in-depth webinar to explain how all of this works. In this webinar, you’ll also learn about:

• Constraint Management: Define limitations upfront to shorten design cycles and reduce errors
• Front-to-Back Integration: Easily transfer logical design to physical layout while maintaining a link to your schematic in case of mid-cycle changes
• Cross Probing: Quickly find components on the board and ensure accuracy and completeness
• Schematic-Driven Placement: Specify component association between an active device and associated decoupling capacitors, as well as the maximum distance between the decoupling capacitors and the power or ground pins on the active component
• Design Reuse and Variants: Reuse existing proven design IP to get your designs up faster while ensuring functionality
• Schematic Validation: A set of checks to prevent common errors when creating schematics

When Is the Webinar?

Wednesday, February 23

08:00 PST / 11:00 EST / 16:00 GMT / 17:00 CET / 18:00 IST/ 21:30 IST (India)

 How to Register?

To register for the webinar:

1. Click Register.
2. Sign in with your Cadence Support account (email ID and password).
3. Select Enroll.

You’ll receive a confirmation email containing all login details after a successful registration.

If you don’t have a Cadence Support account, you can Register Now or go here. 

 
For questions and inquiries, or issues with registration, reach out to us:

• Europe, Middle East, and Africa: eur_training@cadence.com
• USA: Lena Robledo
• India: Preeti P Gowda
• China: Cathy Li
• Japan: Yuji Shimazaki

What’s Next?

• If you find this Webinar useful and want to delve deeper into copper shapes, enroll for the Allegro System Capture v17.4-2019QIR1 (Online) training course, which includes lab instructions and a downloadable design.
• Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails.
• Hungry for Training? Choose the Cadence Training Menu that’s right for you.
• To view our complete training offerings, visit the Cadence Training website.

That’s all for now!