Google FeedBurner is phasing out its RSS-to-email subscription service. While we are currently working on the implementation of a new system, you may experience an interruption in your email subscription service.
Please stay tuned for further communications.
Get email delivery of the Cadence blog featured here
Markets today are being driven by miniaturization. As the size is decreasing, PCB designs are getting more and more complex. Meeting the signal integrity issues and manufacturing boards is becoming challenging. With continuous shrinkage in the pin pitches and spacing, Design for Manufacturing (DFM) checks become vital for optimum manufacturability. Knowing and applying DFM checks are essential to ensure the maximum yield of boards and avoid DFM issues during the complex manufacturing process.
In this post, I will be focusing on DFM issues due to copper void slivers on copper layers. A copper void sliver is a narrow gap in a conductor layer. Spacing rules for shapes do not check for void edge to the same net void edge. Therefore, segments of a void can generate closer than the same net spacing rule based on the object locations and shape parameters. You will definitely want to identify and correct these narrow gaps as they may cause current return path issues and hinder the board functionality. Allegro layout editors provide a gamut of DFM checks to help you deal with manufacturing issues like copper void slivers. By running on-line DesignTrue DFM checks, you can detect copper void sliver issues in an entire design much earlier in the design phase, as they occur. A specific DFM check, Minimum Void Slivers, is available with Allegro® Enterprise PCB Designer Suite and Allegro® PCB Venture that generates DRCs (Design Rule Check) at all places where copper void slivers are formed.
You can use a three-step process to identify copper void slivers in your design.
The value should be according to the DFM guidelines suggested by your manufacturer.
If you already have a CSet defined for your design, you can modify the values in the Void slivers column.
The copper thickness for the plane or signal layer depends on design requirements and may differ from one design to another. Manufacturing processes too will vary for inner and outer layers. You should, therefore, create multiple CSets and assign them to the different layers, as required.
To create multiple CSets and assign them to the layers, do the following steps:
Now that you have assigned CSets, it is time to enable the check.
You can activate this check directly from the Copper Features worksheet through the Analysis Mode option, which is available on right-click when you select the Void Sliver column header. This is how you can turn on or off any check without opening the Analysis Modes dialog. You can run the check any time using the Tools ─ Update DRC command.
To view and verify DRCs, launch the DRC Browser from the Tools menu in the layout editor. It displays a list of all the instances of slivers where narrow gaps are formed by the voids. Selecting a row in the DRC browser zooms to the location of the DRC in the design canvas. You can either fix or waive the DRC depending on the signal integrity requirements of your design.
There are two simple ways to review copper void slivers in a design.
Allegro layout editors are fully capable of controlling the features of shapes. The in-built DFM checks are easy to perform and much more reliable than visual inspection. In just three steps, you can verify and rectify copper void sliver issues, and potentially improve the design turn-around time. Just upgrade your Allegro PCB Designer product to either Allegro Enterprise PCB Designer Suite or Allegro PCB Venture to leverage the power of these advanced DFF checks! If you want to buy, you, of course, have to contact the sales team.