Get email delivery of the Cadence blog featured here
In the days of yore when life was simple, there was a world full of DRAMs (Dynamic Random Access Memory). We have come a long way from there. First came Synchronous DRAMs (SDRAM). Isn't it neater anyway, SDRAM? More systematic and organized, in tune with a clock. But even SDRAM is a thing of the past now. Because we have DDR (Double Data Rate) SDRAM. With SDRAM we fetched data once every clock cycle. With DDR SDRAM we fetch twice that. But did we stop there? No, we certainly didn't. So, we have DDR1, DDR2, DDR3, DDR4, and counting. But haven't we talked about only half the advantages we have with DDRs? Because it's not only data rate that has gone up, power has come down too. Isn't that the closest to any Utopia you can get, almost? Less power and higher speed? What more can you ask? But didn't I say "almost"? In that almost is hidden the toil and sweat of PCB designers.
True, speed has increased. From one word per cycle for SDRAM to eight for DDR4. True, it saves power too, from 3.3V for SDRAM to 1.2V for DDR4 (and we hear it's 1.1 for DDR5). But as ironies are, a strength can itself turn into an Achille's heel. An increase in transfer rate also means an increase in crosstalk and challenges of impedance continuity, not to mention distortions and propagation delay. Similarly, low power also means decreased noise tolerance. So, high speed creates various Signal Integrity (SI) issues and low power introduces Power Integrity (PI) issues. Your products demand a high transfer rate and low power and DDR4 SDRAM fulfills both but you have to grapple with SI and PI issues too.
You can't really have the cake and eat it too. Or, can't you? Today's applications need DDR SDRAM. No two questions about that. But what do you do with the SI and PI issues? And, that's why I am looking forward to the Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level webinar scheduled for March 18, 2020, and thought of sharing the news with all our readers who work on high-performance products necessitating high speed and frequency and low voltage. The webinar will tell us how to minimize DDR supply and DC drop at the PCB/package level, obtain the needed DDR supply impedance profile over a frequency that is low enough and resonance-free, and perform SSN simulation of a DDR bus using power-aware IBIS models. That's useful no doubt because don't we all want to figure out all issues early on in the design phase itself and take action? Saves us time.
When: Wednesday, March 18, 09:00 GMT / 10:00 CET / 14:30 IST / 17:00 CST
Registration closes on Tuesday, March 17.
What all will be covered?
Click here to find out more and to register.
Do let us know how you found the webinar.