DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages, programmable ODT, derating tables, write leveling, and on and on.

Fortunately, the folks working on TimingDesigner and PCB SI have been in close touch with each other and now provide a seamlessly integrated solution that allows straightforward timing closure on even the fastest DDR3 memory interfaces. When timing violations are found, changes can be performed on the PCB design and re-analyzed without any translation making this two tool combination the fastest path to timing closure.

Due to repeated requests for such a solution, a joint company (Cadence and EMA) webinar will be broadcasted and recorded on June 9, 2010. Please register at your earliest convenience so that you will not miss the opportunity to watch and ask questions. Additional information and registration is available from this link.

Let us hear your feedback on the webinar.

TeamAllegro