DesignCon 2019: Is this the Year?

2019 has started --- is this the year of advanced packaging, where system design enablement shifts to the package? If you are attending DesignCon (designcon.com) in Santa Clara, California, in a few weeks, there’s a robust agenda, and it might be hard to figure out what to see. Let me give you a few hints so you can bring back useful information that can help with your next design.

• Stop by Cadence booth #711 (to the left as you enter the exhibit area) and learn how you can address your design challenges with advanced IC packaging and cross-platform solutions for next-generation 2.5D and 3D-IC design. You’ll  learn about the latest technology that further improves the integration between Cadence Virtuoso IC design tools, Allegro packaging tools, and Sigrity analysis solutions. You’ll also learn the latest about the TSMC reference flows for InFO (FOWLP), CoWoS (2.5D) and WoW (3D). Finally, find out how Cadence is enhancing OrbitIO Interconnect Planner for cross-domain planning, management and optimization of chips, packages, and boards.
• We also hope you will drop by the Great America Ballroom, upstairs, on Thursday, January 31 at 2:50pm to hear Samsung Foundry discuss an Advanced Package Design Sign-off Reference Flow.  And right after that, discover how to tackle the issue of connectivity planning and management at the system level with System Planning and Management for 3D Designs.