Designing Integrated SOI X-Band Radar Switches with Cadence Workflow

27 Jul 2026 • 3 minute read

RF systems operate under tight budgets for loss, coupling towards unwanted paths, timing control, and power handling. As the radar and wireless infrastructure market moves toward more complex and higher-performing hardware, RFIC designers face increasing pressure. Transmit/receive (T/R) switches are core elements of time-duplexed RF systems, and must simultaneously meet aggressive requirements on insertion loss, isolation, power handling, and switching speed, while remaining manufacturable at scale. The massive silicon manufacturing ecosystem and the best-in-class RonCoff figure of merit performance rating of silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies offer an attractive solution for novel T/R front-end switches. However, the low-voltage device breakdown requires stacked circuit topologies that degrade switching-time performance.

Fabless semiconductor company LintrinsIC Semiconductors Inc. has developed a patented approach to solve the typical tradeoff between power handling and switching time with tailored analog/RF circuit solutions that enable high-power SOI switches to enter the X-band radar market with best-in-class overall metrics. Achieving first-pass success for these types of designs requires an EDA-integrated simulation workflow that encompasses analog domain analysis for the integrated circuit, tightly coupled to package and PCB level electromagnetic (EM) and thermal modeling.

Giuseppe Michetti, CTO of LintrinsIC, presented at CadenceLIVE Silicon Valley 2026 an end-to-end EDA-driven workflow that converges circuit design, EM analysis, thermal modeling, and package/PCB co-design in a Cadence Virtuoso/Clarity 3D Solver/Sigrity X implementation that enables designers to centralize and model chip-level components, as well as packaging and board design.

Technology and Modeling Challenges

The figure below is a simple depiction of how a radar system works. The radar pulse goes through a switch, into an antenna, and then in the air hits a target. As the pulse comes back, if the switch is now in the other position, the pads can be decoded with the time and switch setting information, which can be used to uniquely track the target in space. Focusing on the role of the switch in the system, you can see that the earth path goes through the switch twice. By improving the loss in the switch, system performance increases.

The system needs to be both agile and reconfigurable at the same time, so the switching speed in some scenarios is crucial in determining parameters. To reach targets that are further out in space, more power is needed, so this switch needs to be able to withstand this power without introducing distortion. The switch is at the core of this system, and because of the many requirements, the design is typically over-constrained, and only a few technologies are suitable for this complex design.

Cadence Flow for RF/Thermal Modeling

Using the integration capability of Cadence’s Virtuoso Layout Suite, Clarity 3D Solver, and Sigrity X platforms, a 3D finite-element method (FEM) EM model can be extracted directly from Virtuoso layout data. The same model can be reused for thermal performance estimation and backfitting in the Virtuoso netlist. This approach captures first-order effects that are absent in foundry PDKs, including package-driven isolation degradation, bandwidth limitations, insertion loss underestimation, and temperature-dependent power handling.

The LintrinsIC CadenceLIVE presentation describes this methodology using an LT0001 X-band SOI single-pole double-throw (SPDT) switch in a 4x4 quad flat no-lead (QFN) package. Measured hardware results show strong correlation, demonstrating the effectiveness of an integrated EDA workflow for RF and packaging design.

Conclusion

Design flow optimization is crucial for silicon success in RF, and conventional analog/IC tools are limited in the degree of optimization sophistication they provide. The unique, patented approach LintrinsIC has developed that leverages the Cadence Virtuoso/Clarity/Sigrity workflow solves the typical tradeoff between power handling and switching time and is delivering promising hardware correlations results.

To learn more about this flow and the technology behind it, you can view the presentation on the CadenceLIVE Silicon Valley 2026 on-demand page.