Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your Job Easier!

As these types of designs see an increasing number of applications and design starts, we need tools that make it as easy and efficient as possible to turn them from a specification to a finished layout. Whether you get seed information in GDSII, DXF, artwork, or another format, you need tools to turn raw geometry objects into an intelligent layout, apply technology rules, constraints, and a netlist, and then complete your design.

With the seventh QIR update release of 16.6, Cadence APD and SiP Layout XL tools offer you a host of tools that make your task easier than ever. This quarterly update made the WLP design flow a priority just for you. To learn about some of the exciting new tools that have been added, upgraded, and productized, read on!

Upgrades to the “Compose Die from Geometry” Tool

First up, let’s look at the upgrades to commands you are already familiar with. In particular, the compose die from geometry (Add -> Standard Die -> Compose from Geometry…) adds exciting new capabilities.

It continues to turn raw geometry objects like rectangles, shapes, and text into a die component and symbol, but you can now import pin numbers and even create/assign nets to pins based on text from your source geometry data. Talk about time savings! Remember that netlist that we needed to apply to the design once we had component pins and plane shapes in the layout? Check that item off your list with ease with these enhancements!

What if your GDSII data didn’t come with text to indicate pin numbers? If those pins aren’t on any well-defined grid, applying one of the symbol-editing application mode’s host of automatic pin numbering patterns may not give just the right ordering of numbers. Never fear! A late addition to the QIR has a beta feature for interactively renumbering pins by individual pick or dragging a path through them to establish the ordering. Look for more information about this command in an upcoming post, or enable it in your user preferences and give it a whirl to see what it can do for you.

Conversion Tools for Routing Productized

Components aren’t the only objects that you need to reconstruct from polygons and lines coming in from some manufacturing data. Polygons or lines on a manufacturing/documentation layer may represent routing clines. Shapes may indicate placement of vias and bond fingers. In custom designs, you may even have odd shapes that represent complex padstack pads; maybe that L-shaped polygon is really supposed to be a fiducial and needs to be turned into a library pad shape for use in a via or a pin—but creating a pad shape symbol from it is difficult without the context of the rest of the design. Or, it is possible you even need to create shapes on different layers based on pad shapes plus an expansion/contraction value.

Whatever your source shapes and lines represent, a brand new set of commands found in the Tools menu under the “Convert” heading, offer you all the capabilities you need. Choose from the shape to cline, shape to padstack, shape to via, and pad to shape tools to get your layout looking the way you want and ready for optimization and DRC rule checking. Just one of these—the pad to shape tool—is shown below to whet your appetite.

All these commands have been turned into production features from their earlier status as beta tools based on your use, feedback, and comments.

… and a New Shape Voiding Tool, Too!

Now that you’ve converted your basic shapes and structures into intelligent objects, what about managing your plane and large conductor layer shapes? We’re all familiar with dynamic shape voiding and cross-hatched shapes. And, by now, you have probably mastered the degassing and thieving tools.

But what about those cases where, for signal integrity, power, or thermal reasons, you need to create voids around an object on a DIFFERENT layer than the object itself is on? Do you need to void the plane shapes above and below the vias and clines of a critical differential pair or high-speed bus? What about creating merged void outlines around specific critical net pins on one or more layers when your global shape voiding parameters are configured for individual voids for pins?

Enter the brand new “void adjacent layer shapes” tool. New to the Shapes menu (look for it near the Delete Islands entry, and check out the UI for it above), this command will have you managing those complex object-void relationships across all layers of your substrate with power and ease you never would have hoped for before!

Have an Idea for Making this Flow Even Easier?

All these upgrades and new commands are there to streamline your flow. With them, you’ll have your package substrate finished faster with fewer errors and more intelligence than ever before. But, there is always room for improvement. If there is still an aspect of your flow that causes you nightmares—or just takes more time than you think it should—be sure to let your Cadence support representative know. We’re all ears—maybe in the next QIR update, you’ll see your idea and be able to realize even more time savings!