Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

9 May 2019 • 2 minute read

As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the innovation and speed performance trend going forward in the electronics industry. Advanced packaging, itself, has experienced tremendous advancements in technology, materials, and processes, enabling high-performance complex systems to be successfully manufactured with favorable yield and cost advantages compared to traditional SoC implementation.

Figure 1: Overview of the SI/PI challenges; source: Samsung Foundry

Nevertheless, with complex high-performance advanced packages, you are faced with Signal Integrity (SI) and Power Integrity (PI) issues due to fast IC data transmission speeds combined with lower power supply voltages and large processing power demands. High-speed parallel interfaces (HPI), such as in High Bandwidth Memory (HBM), have different signal integrity challenges compared to high-speed serial interfaces (HSI) and when you include AC and DC power integrity requirements, it can be daunting for an engineer to sign-off on the advanced package design without following a certified and correlated reference flow.

Figure 2: Cadence Package Design/Sign-off flow; source: Samsung Foundry

Last year, Cadence in collaboration with Samsung Foundry announced the industry’s first advanced packaging reference flow for Samsung Foundry customers. During this year’s CDNLive, Silicon Valley (CDNLive2019-SV), Samsung Foundry’s Dr. Sylvie Kadivar and Dr. Max Min presented details of the Advanced Package design and sign-off reference flow covering all the various SI cases with HPI, HSI, and AC and DC PI requirements. The complete Cadence Advanced Packaging flow is certified and correlated to the Samsung golden flow using Cadence’s Allegro, Sigrity, Voltus, and Spectre technologies and was verified with memory interfaces, high-speed interfaces, and a core Power Delivery Network for CPU and GPU through both FO-PLP and Silicon-interposer 2.5D package-based test cases.

This paper was also presented at DesignCon (DesignCon2019) by Samsung Foundry’s Dr. Sungwook Moon.

With the Advanced Package reference flow, joint customers of Cadence and Samsung now have a proven documented step-by-step approach to validate and confidently sign-off their advance package designs to enable first-pass success. Click here for the details of the CDNLive presentation from Samsung Foundry.

Team Sigrity

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