High-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X

2.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain continuous growth in computing performance, advanced packaging technologies are constantly evolving. TSMC's System-on-Wafer (TSMC-SoW™) technology and its highly advanced design necessitate a reliable and efficient high-performance electromagnetic (EM) analysis tool.

Design Optimization for SerDes Beyond 200G Interconnects and PDNs with Clarity 3D Solver

CadenceLIVE 2026 included a presentation by Cadence customer Global Unichip Corp. (GUC) discussing how GUC uses Clarity 3D Solver and Sigrity X PowerSI analysis technologies to perform signal integrity/power integrity (SI/PI) simulations for high-speed key IP on SoW-X, including serializer/deserializer (SerDes) 212G, GUC's Universal Chiplet Interconnect Express (GUCIe) D2D 64G, and more. An example is provided showing how the Clarity solver is used to analyze the signal integrity of the SerDes 212G signals on SoW-X. Through the visualized EM field provided by the tool, the near-end crosstalk (NEXT) at the micro bump (μBump) and ball-grid array (BGA) interfaces is strengthened from approximately −46dB (failed spec. −65dB) to about −74dB (pass spec.), while the far-end crosstalk (FEXT) is improved from approximately −27dB (failed spec. −40dB) to about −60dB (pass spec.).

S-Parameters Correlation Between Third-Party EDA vs. Clarity 3D Solver

The figure below compares the S-parameters extracted by the Clarity 3D Solver with those from a third-party 3D full-wave solver, showing very similar trends between the two approaches.

The discrepancy in the worst-case SDD21/SDD11 at 53GHz is within approximately 0.6dB, while the difference in NEXT/FEXT at 53GHz is within 0.2dB. Notably, compared to the third-party 3D full-wave solver, Clarity extraction not only provides results similar to those but also achieves about a 15% reduction in runtime when handling scenarios with dozens of SerDes physical layers (PHYs).

SerDes212G PDN Loop Inductance Analysis and Optimization

For the SerDes 212G power delivery network (PDN), GUC designers solved their PDN concerns using Sigrity X PowerSI technology to optimize the loop inductance of the worst-case domain from 337pH, which exceeds the specification limit of 300pH, down to 287pH, bringing it within specification. After optimizing the PDN from the front-side redistribution layer (RDL) to the backside, all five power domains met the constraint of the loop inductance of <300pH, as shown in the figure below.

Conclusion

TSMC's SoW-X is a novel advanced packaging and heterogeneous integration technology that satisfies the demands of HPC and AI applications through the benefits of elevated computing performance, power savings, and area optimization, and more, as well as the tight integration of μBump to BGA, local silicon interconnect (LSI), RDL, PDNs, and voltage regulator modules (VRMs). The optimization strategies (e.g., main route, BGA area, planes, and vias) discussed in this presentation provide insights and guidance for SoW-X design integration.

GUC uses Cadence multiphysics solutions, i.e., 224G-SerDes, UCIe-64GT/s, HBM4, and SoC logic core power rails to successfully meet SI/PI constraints of SerDes above 200G designs. The signal/power integrity analysis in this presentation has been well verified by Cadence's Clarity3D Solver and Sigrity X PowerSI.

To see the full presentation, visit the CadenceLIVE 2026 Silicon Valley on-demand webpage. To learn more about Cadence's tools featured in the GUC presentation, visit the Clarity 3D Solver product webpage and the Sigrity X product webpage.