BoardSurfers: How Many Test Points are Enough for Effective In-Circuit Testing?

Many PCB engineers have nightmares about retrofitting test point pads into their perfectly arranged designs following a final review with senior experts.

When I started my journey in PCB design many years ago, the internal design rules document stated that “every net must have a test point.” Enforcing this rule was a challenge. This raises the question: how many test points are enough?

The problem with test points is that they exist in an alternate reality compared to the spacing constraints of a PCB design. Until a few years ago, our test point center-to-center spacing rule (TP to TP) was a whopping 2.54mm. This seems excessive, especially when I can place discrete surface-mount device (SMD) capacitors as close as 0.4mm apart without many complaints from the PCB assembler. While it depends on the assembler, even a spacing of 0.5mm for components is generally considered safe.

In further contrast, the most basic PCB supplier is probably comfortable with a trace width and line spacing of 0.15mm. When accounting for soldermask pads, an extra space is required for the pad-to-trace distance; however, this will generally not exceed 0.2mm from trace to pad using older soldermask processes. So, why is the increased spacing required for test points? Why do we need to space them farther apart than almost any other footprint on the board?

The parallel universe refers to the mechanical aspect of testing. For every test point on the PCB, there is a mechanically spring-loaded pin that crashes into your world to establish contact with the board. The In-Circuit Test (ICT) fixture, often referred to as the “bed of nails” for the assembly process, is sourced from a specialized supplier that excels in that area. However, physical limitations exist to how closely these ICT pins can be placed. Each pin must be mechanically fixated at precise locations to ensure it touches the board within the tight radius that you have provided it. What radius are the test point pads you chose? Because this is the specification that your ICT fixture supplier now must work with.


Image credit: Q1Test Inc., a bed-of-nails clamshell tester capable of probing top and bottom

The location of the test pads is just one challenge, but an even greater concern is the mechanical skew. Since retesting of PCBs will be necessary, the testing equipment must repeatedly engage with the PCBs without degrading results. This is only possible with a robust physical structure surrounding the test pins. Several layers of reasonably thick material with special e-safe properties are used to hold each spring-loaded cylinder in place. This material governs the limitation of the TP-to-TP center spacing; you can only drill support holes so close together until this material fails under repetitive strain. If the material is damaged, the pins can become misaligned, risking the possibility of missing the test pad or, even worse, creating a short. This is the reason for setting 2.54mm center-to-center spacing for standard-sized probe cylinders. After interviewing our fixture suppliers a few years ago, we were able to reduce this spacing to approximately 1.7mm, thanks to improved modern processes and materials.

So, how many test points do we need to incorporate? For beginners, I recommend including test points in your design from the very first revision. This is the best way to ensure they are integrated into the design and do not get canceled right before it is productized because they do not fit in. I am sharing a true story. On my first-ever hardware project, I received guidance from a highly experienced hardware team leader. I have never forgotten the advice he offered me regarding ICT testability: He said, “If any of our schematic designers ever instruct you to design a rev00 PCB without any test points but to place them in on the next revision, just slap them!" Clearly, he jested, but the intended meaning remained.

To determine how many test points you need, you must understand “why” you are adding them. ICT is generally intended to provide a quick check to verify the assembly builds. Even Wikipedia will tell you that the goal of ICT is to check for shorts, opens, resistance, capacitance, and other basic quantities, showing whether the assembly was correctly fabricated. ICT is not intended to serve as a final test.

In scaled electronics manufacturing, the “Final Test” is a separate stage from ICT. ICT is crucial for identifying any issues that may arise during production. For instance, you want to catch the scenario when someone places an incorrect resistor reel on a pick-and-place machine on the assembly line or when a wrong variant (say, variant B) of an assembly program is selected and incorrectly placed an expensive extra chip. What if last year’s PCB revision was retrieved from the storeroom or if a diode or LED is placed with the wrong orientation?

Catching these potential mistakes early on is extremely important, as it can save a significant amount of time and money by reducing the need for extensive rework or material scrappage. ICT offers an extremely fast method to check these critical factors as quickly as possible.

Multiple PCBs can be tested simultaneously in a multi-way panel at very high speeds. The final test, in contrast, is relatively slow. During the final test, the electronics must communicate with each other, exchanging messages through a handshake process. The speed of this communication is gated by both the device under test (DUT) and the final test equipment or fixture. Electrical parameters are tested, input levels are ramped up and down, and output waveforms are analyzed for timing and other criteria to make sure that the product meets its specified requirements. While there are often multiple final test machines located at the back end of a production line, there is only one ICT machine in the center.

To effectively reduce the number of ICT test points in a design, consider the following examples:

• If ten resistors have the same value on the PCB, is it critical to have two ICT pins for every resistor on the board?
• Consider a scenario where a capacitor is in parallel with a significantly larger value capacitor. Does it make sense to add extra test points for this? Smaller capacitor values can be shadowed, especially those with values small enough to fall within the tolerance range of the larger component.
• When two resistors are connected in series, you can eliminate one test point by measuring across both resistors. This approach is effective if the resistor values do not shadow each other.
• Do we really need to check the orientation of all diodes and LEDs? If the program places one component correctly, the others should also be correctly positioned if they have the same part number.
• Usually, a series resistor is placed in an LED circuit. It might be prudent to place just two probes to test this as a series circuit, eliminating the need for a test point at the base of the diode. The same reasoning can be applied to transistors.
• What about direct chip-to-chip communication lines, such as Serial Peripheral Interface (SPI)? If there is no series resistor between them, do we even need a test point on each one of these internal connections? What tests can be performed? Perhaps none. It is advisable to discuss this with your ICT engineer, as there may be some IC pins that we can safely probe to perform, like a tristate buffer check. However, do expect that for many IC pins, a test point may not make sense at all. If saving space on your board is a priority, have a conversation with your test engineer.
• Resonators are not generally tested by ICT, so we don’t bother putting probes there. In a previous project I was involved in, we encountered a problem with a resonator’s tolerance. The resonator’s frequency could not be directly tested as the probes themselves interfere with its operation. It was wisely decided that timing should be checked by some internal communication lines between chips. The frequency timing of these lines was directly proportional to the frequency of the resonator.
• Does your assembler use Automatic Optical Inspection (AOI)? This machine visually checks the quality of soldering on component joints and also verifies the presence of components. So, why do we need to check 100% for component presence using ICT? AOI machines can also read or compare text written on certain parts to catch if any wrong component has been placed.
• Regarding PCB shorts, it is essential to ensure that you ask for a 100% electrical test from your PCB fabricator for every board you receive. This is the fabricator’s equivalent to ICT for the bare board. PCB fabricators have machines that can perform electrical tests very quickly on all adjacent lines to check for shorts, resistance, and opens. This should be a standard quality check for all your PCBs. Furthermore, these tests should be documented and stored as certification for each delivery. Do not accept low-quality PCBs from your supplier. Some fabricators offer lower prices if they can include a certain percentage of defective PCBs in your order. Accepting this is a false economy and a flawed paradigm.
• High-end design projects can afford the cost of a special test-pin jig for certain types of chips, which can be integrated into the ICT fixture. These jigs provide a custom high-density probe arrangement that surrounds a specific integrated circuit (IC) type and contacts directly with the surface mount device (SMD) pads. This approach saves space and significantly reduces the number of test points needed in the surrounding design. However, it does increase the cost of the fixture, its durability, and its lifespan.

In a moment of wisdom, I realized that we do not need an ICT probe for every test pad of every single PCB. The fundamental problem of test point density stems from the large spacing required between probes. In contrast, the PCB fabricator has no issues placing copper pads just 0.3mm apart, edge-to-edge. However, ICT engineers operate in this macro-realm and prefer wide spacing between test points. To address large spacing requirements between probes, it is possible to test PCB A using one class of test pads and test PCB B with a different class of pads, with both sets residing on the same PCB. This approach allows us to minimize both the ICT fixture spacing and the PCB pad spacing while ensuring that 100% of components are potentially tested on each board. To do this, we can employ two different ICT fixtures to test the same board. Alternatively, a single ICT fixture could be designed to test a panel of PCBs, using a different arrangement of test probes for each individual PCB, depending on its location within the panel.

I invite experienced designers to share their insights, experiences, or feedback in this area. Your perspective will be especially useful for our young engineers entering this PCB world. Let us pass on our wisdom so that they understand the struggles of times, past and present. All comments are welcome!