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Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim” and is one of the major classes of signal integrity (SI) problems that can exist in the Printed Circuit Board (PCB) designs. Reducing crosstalk as much as possible is always beneficial to a PCB design. Running crosstalk simulations using specialized tools is often a time-consuming endeavor requiring specialized knowledge and an understanding of the driver and receiver model details. Using the Allegro® In-Design Analysis (IDA) Crosstalk Workflow, PCB designers can run crosstalk simulations using IBIS models directly in the PCB canvas where they can diagnose and quickly fix crosstalk issues.
Crosstalk issues can be caused by trace geometry or return path issues in a design. Both of these issues can be diagnosed using the Crosstalk workflow. Crosstalk simulations are performed using the Sigrity hybrid solver. You can specify the IBIS models for the driver and receiver or use the default models provided. The simulator looks at all of the combinations of the victim held low or high, and the aggressor switching towards or away from the victim to identify the worst case. As shown in the below example, the amount of Crosstalk in milli-Volts (mV) on each victim net is given in the table. For the worst-case nets, you can run a more detailed simulation to see how much crosstalk each aggressor net is contributing. By identifying the biggest aggressor, you will identify the smallest changes needed to make the biggest impact on reducing crosstalk. In this case, moving the BL_SINK2 net away from the victim will have the biggest impact on reducing crosstalk. The results can be exported to a spreadsheet to easily share outside of the Allegro layout editor.
The Allegro IDA Crosstalk Workflow has taken a complex analysis typically only possible with specialized tools run by experts and has put it in the hands of the PCB designer to resolve issues directly in-design.
Click here to watch a short demo of the Crosstalk Workflow in action.
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