BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t have the time to confirm that these constraints lead to impedance values that are within the required margin for their designs. High-speed traces on a board are laid out most carefully, but the remaining traces are often sent for manufacturing without any inspection after routing. Allegro® In-Design Impedance Workflow powered by the Sigrity hybrid solver allows the entire post-layout board to be analyzed quickly and easily to avoid costly layout mistakes that can cause a board re-spin and delay a project. Anyone with Allegro® PCB Editor can run this analysis through the Workflow Manager and view impedance results directly on the Allegro PCB Editor canvas. The full cross-sectional geometry is used to compute accurate impedance results presented in a table with characteristic impedance, delay, and RLC values for each net and segment within a net.

The DDR signal bus shown here runs over a split reference plane, and one net is falling in the gap between the reference shapes. The Impedance Vision shows a roughly 3x impedance change for this net which will lead to huge reflections at the driver and receiver, potentially requiring a board re-spin to resolve. From the Impedance Table, you can easily sort, filter, and cross-probe to the canvas to quickly pinpoint and fix problem areas. In this case, the DDR trace can be moved up or down to avoid the reference gap.

The Impedance Workflow will also identify nets or segments where no reference exists at all and impedance cannot be calculated. In this way, the Impedance workflow can help designers avoid issues that might not appear as constraint violations. For most designs, the analysis takes seconds to run on all signal nets. The results can easily be exported as a CSV file, making it possible to quickly create post-layout reports and share your design details outside of Allegro PCB Editor.

Click here to watch a short demo of the Impedance workflow in action.

You might also be interested in the following links:

• Sigrity Tech Tips: A library of informational videos with helpful tips on using Cadence® Sigrity tools for signal integrity (SI) and power integrity (PI) tasks.
• Cadence Sigrity Aurora: Traditional signal and power integrity (SI/PI) analysis for pre-, in-design, and post-layout PCB designs.
• So You Think You're an Expert: Learn about impedance matching of transmission lines.