# Implement SI and PI in High-Speed Memory Interfaces

Signal integrity (SI) engineers tasked with successfully implementing memory interfaces, such as DDR4 and DDR5, face major challenges in meeting the requirements in a timely fashion. The traditional design workflow typically assumes an ideal power distribution network (PDN) without including the undesired effects of coupled signal, power, and ground planes that invariably impact PCB SI. When analyzing power integrity (PI) and SI issues separately, power-based SI issues such as simultaneous switching noise (SSN) can also crop up causing failures (** Figure 1**).

*Figure 1: Typically, SI and PI analyses are performed separately wherein SI analysis assumes an ideal PDN. (Image: Cadence Design Systems)*

However, there is a wider scope to consider for accurately perceiving the effects of the I/O data signals (SI analysis) and the power and ground planes (PI analysis) in high-speed DDR memory interfaces. These, in fact, are not the separate issues as they are often viewed to be; the non-ideal PDN invariably affects some of the most common SI analysis parameters, including reflection, crosstalk, and timing.

Understanding Power-Aware SI

Power-aware SI not only considers the non-ideal data signals but also the non-ideal PDN. For instance, noise in the PDN primarily affects the system jitter performance ― pushing further constraints on an already-tight timing budget of DDR interfaces.

Typically, it is assumed that the power and ground planes are identical for computing the characteristic impedance in a 2D simulation. Plane bouncing, or the variation of the potential difference between the power and ground nodes across the surface of the planes, couples with the reflections from a trace impedance mismatch. Any coupling between the power/ground plane and data traces leads to crosstalk. Ultimately, crosstalk affects timing because it is a measure of the undesired movement of energy from one trace to another. Reflections also cause delay changes and affect the timing.

*Figure 2: Ideal power ground vs. Non-ideal power ground*

Simultaneous switching signals on the DDR4 and DDR5 data bus with a non-ideal current return path can cause SSN. Each bit in the parallel data lines can act independently of one another, potentially creating instances of greater load on the power rails when the signals toggle simultaneously. This “simultaneous switching” can cause a droop in rail voltage, which, in turn, raises the ground voltage to a non-zero value within the device.

Ultimately, SSN adversely affects the analysis of random jitter in eye diagrams as well as generates additional constraints in optimizing the system noise margin for DDR memory. Typically, SSN analysis can be performed only by an analysis tool by utilizing both special I/O (power-aware IBIS 5.0+) models and interconnect models (coupled signal, power, and ground).

While the IBIS 5.0+ models can be extrapolated from the memory controller and memory provider, the power-aware interconnect models are extracted from a completed design. Classic SI tools are not equipped with the right field solvers to adequately complete the task of SSN analysis. Moreover, once a design is completely laid out and routed, it is difficult to turn back and optimize while meeting deadlines.

Traditional design rule checks for most commercial simulation platforms do not account for noise effects on the signals, with only a geometrical rule check. This makes it difficult to detect any “power-aware” violation of design constraints or to fine-tune SI/PI issues during the in-design and post-layout analysis.

The following sections provide a more detailed treatment of each step in the flow in the power-aware SI analysis.

Power-Aware Design Rule Checks

While many engineers would like to use a full-wave 3D tool for interconnect extraction, typically, power-aware analysis uses S-parameters created with a hybrid solver. Engineers often resort to hybrid solvers that utilize a field solution, circuit equivalent model, or both. With time domain SPICE-like simulators, a simple lumped-element (RLC) broadband SPICE model is extracted from the frequency responses obtained via simulation, which results in a simplified mathematical representation of the passive input/output system behavior.

While the speed in obtaining simulation results is cut down drastically from a full-wave 3D approach, it often leads to less accurate modeling at higher frequencies; particularly for the multigigabit channels with complicated structures found in DDR interfaces (*e.g.*, serpentine line, transitions, back-drill, etc.). Moreover, extracting time domain simulations from the large interconnect models can cause convergence issues as S-parameter models do not have information at DC and may not behave at lower frequencies.

The “cut and stitch” approach offers an alternative to the lengthy 3D full-wave and less accurate hybrid solvers by dividing areas of interest into partitions where an engineer can select any solver of choice to accurately model a section of PCB. This way, the portions of the PCB that require more complex analysis can be modeled in 3D full-wave while saving hours of time modeling less desired sections with hybrid tools. However, while this does save time on model generation, an engineer would still ultimately have to extract a SPICE model every time corrective adjustments are made in layout in order to understand the power-based SI variations.

The FDTD Approach

The finite difference time domain (FDTD) method removes the use of S-parameter extraction and the potential convergence issues that come with them. Instead, the FDTD method is leveraged with a hybrid solver to obtain time domain results that include the interactions between signal, power, and ground.

The Sigrity SPEED2000 engine can be used directly from Sigrity SystemSI using the FDTD-direct method with a hybrid solver by integrating a circuit solver, transmission line solver, and a fast electromagnetic (EM) field solver to analyze time-varying interactions between data and power/ground planes (** Figure 3**). Linear excitations are given to a large number of signal nets to report signal quality with coupling noise. This eliminates the need for large S-parameter files and nonlinear analysis without compromising on data accuracy.

Augmenting this typical design workflow at extraction with a hybrid solver utilizing the FDTD method can allow an engineer to rapidly analyze and assess any power-aware SI issues without the need to repeatedly perform model extraction. This ultimately yields more accurate simulation results at the PCB/IC package level with both accuracy and speed for an overall quicker time to market.

The benefits of this can readily be seen In a DDR interface for instance, where the high routing density already creates complex layout problems in length matching, spacing, and data signal grouping while meeting crosstalk, timing, cost, and space constraints. Sticking with conservative line lengths and space may fulfill crosstalk and timing specifications but will create a bigger board.

Also, traditional SPICE time-domain simulations typically have more pronounced non-passive and non-casual issues due to the large number of DDR signals, DDR power/ground nets, and decaps included in the simulation. Implementing an FDTD method with a hybrid solver can allow for more accurate simulation results that match the lab results with a quicker time to market, adding the ultimate level of signoff using 3D models for the full DDR bus interface.

Final Signoff with 3D Full-Wave Modeling

*Figure 3: To evaluate Simultaneous Switching Noise (SSN), interconnect models must include signal, power, ground structures and the coupling between them.*

For accuracy, memory buses need to be extracted in their entirety with power and ground. More often than not, this has been too large a job for most 3D full-wave modeling tools and causes convergence and stability issues; advanced multi-chip DDR interfaces could involve the simulation of hundreds of ports.

In the finite element method, convergence is typically reached by perturbing a solution into smaller time steps to produce smoother output curves against a tradeoff of the simulation time. Stability relates to the decay in the error as the simulation progresses with every step. A solution needs to exhibit both stability and convergence in order to reach an agreement between the solution of the partial differential equations and the computed solution found with the discretization process.

Due to the lack of computational resources to adequately simulate a large DDR interface, designers who choose to use 3D full-wave extractions quite often segment their design into smaller pieces. This requires a high level of expertise and can be prone to errors. Moreover, this method also does not typically lend itself to an iterative design process — if changes are made in the layout, model extraction must be performed before rerunning the simulation.

That is changing, however, with the availability of Clarity 3D Solver that delivers faster simulation performance and unbounded capacity compared to legacy field solver technology (** Figure 4**). It’s optimized to distribute a job across multiple low-cost computers while remaining equally efficient when running on a more powerful and expensive server with terabytes of memory.

*Figure 4: Clarity 3D Solver efficiently matches the available computing resources to the size of the design. (Image: Cadence Design Systems)*

That allows Clarity 3D Solver to create highly accurate S-parameter models for use in SI and PI analyses. Furthermore, Clarity 3D Solver eliminates risk of manually reducing the size of structures being modeled.

Conclusion

The DDR4 and DDR5 interfaces involve the most challenging SI problems that engineers face today with an increase in data rate to gigabit speeds, tightening the timing budget. The multi-gigabit parallel bus interfaces involve declining voltage swings, equalized transceivers, tight bit error rate (BER) targets and matched transmission line lengths. Understanding the effects of a non-ideal PDN on SI is no longer optional in order to meet the tight timing constraints.

Using the traditional SI analysis workflow, this can often be a cumbersome process as power-aware SI analysis is often done post-layout where every change in layout would require repeated model extractions in order to adequately understand the SI effects from fluctuations in power and ground rails. A proven front to back flow will minimize design iterations and help get products to market on time and on a budget.

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