Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability with Latest 16.6 ISR of Cadence SiP Layout

As package substrates continue to get more complex, often resembling silicon as much as traditional organic substrate, design rules get tighter, manufacturing concerns become more important, and the simple act of ensuring that high yield, high reliability is a fact of life that becomes anything BUT simple.

The APD and SIP Layout tools provide a robust set of online DRC checks around spacing and physical characteristics, complemented by an equally comprehensive set of assembly and electrical constraints. Cadence even allows you to extend these core rules with advanced constraints and custom-developed RAVEL rules.

Even said, though, all of the above checks run on the substrate as it is designed in the database. What about checks designed to run on the manufacturing data exactly as it will go to production? That’s right. We’re talking signoff DRCs run against your final GDSII data.

Whether you’re validating spacing clearances post-vectorization of all circular pads and other arc segments (Hint: be sure to take advantage of the new vectorizing strategies available in stream out to eliminate spacing errors caused by this conversion process!), or you’re ensuring that metal density is exactly to spec, nothing beats the PVS formal verification tool for offering you the confidence that everything is just right in your design.

Download the just-released ISR of 16.6 (available today, August 28). Then, in SIP Layout or APD (using a SIP Layout license), you gain access to this brand new ability to import your PVS DRC report. View errors, correct them, and speed your way to meeting all your most advanced sign-off rules.

To learn more about this exciting new offering, keep reading!

Importing PVS Rule Violations

So, you’ve generated GDSII data from your SIP database and run it through your PVS checker. You’ve got a DRC db file with the results. What next, you ask? Check under the Manufacturing menu. There, you’ll find the “Import PVS DRCs” entry under 'Unsupported Prototypes'   (more on this at the end of the blog)

Select this command, or run “import pvs drcs” from the command line, and you’ll be asked to browse to the DRC database output file from PVS. Select it and that’s it. You’re done! The file will read in. Each rule that has violations in the database file will get its own layer created on the manufacturing class. On that layer, DRC markers will be created and the region or line illustrating the problem area or gap, will be shown. In addition to that, you’ll get a report of what rules were read in, the layer they were mapped to (don’t worry, we understand that your PVS rule names can get much longer than the maximum layer name length in your SIP or APD database!), and how many errors for that rule there were.

Because PVS rules don’t have a 1:1 correlation with the conductor layers in your original design, and since they are defined on manufacturing layers, you might worry that all the DRC bowtie markers will blend together. Not so, though. Set the user preference option “icp_import_pvs_beta” and when you turn off the manufacturing layer associated with a rule’s DRC markers (such that the reference region/line markers are invisible), the DRC bowties will automatically hide in the display as well. This allows you to easily see only one rule’s markers at a time.

And guess what? Just like any other external DRC violation marker, you can walk through the violations using the Constraint Manager interface—complete with cross-probing, selection, and show element. How’s that for easy, consistent access to all your DRCs, regardless of source?

Can I Directly Run PVS on my MCM/SIP Database?

You certainly can! But, because the PVS tool is only available on Linux, you will need to be running your package design tool on that same platform if you want to take your integration with the signoff rule checker to that next level.

If you do happen to be running on Linux (and have licenses of PVS available to you), then you’ll notice an additional menu entry directly above the Import PVS DRCs we just spoke about. This one, however, is labelled “Run PVS DRC…”. Click on it, and you’ll see a dialog window come up that looks just like the following:

From here, you can specify the PVS rule deck to be run, and the stream-out layer conversion file name and output file. If you are making use of the option to save your stream out settings with your database (see the “stream_out_save_options” entry in your user preferences), then the tool will even make sure to match this interim GDSII output with what you will use in your final output by looking up your last stream out run settings.

Once you’ve got things set up, press the Run button at the bottom of the form and watch the magic happen. When PVS has finished, you’ll have your design freshly updated with its results, ready to make any changes necessary to get your substrate DRC-clean and ready to be sent for manufacturing.

What’s Next for Formal Verification DRC Support in SIP and APD?

Don’t let the location of these commands under the 'Unsupported Prototypes' classification deter you. We just want your feedback before we move them to official production features or add-on options -- their status, access and location may change in future releases. We’re looking to you, our valued design community, for suggestions on other enhancements you would like to see here. Maybe you want the import interface to first list the rules that have violations in a grid, so you can filter which DRCs are imported into the layout design. Or, it could be that you want the option to supply a file mapping the long PVS rule descriptions to short friendly names to be used for the layers and DRC marker violation titles in the database.

Whatever the case, contact your Cadence support representative today with your ideas. We’d love to hear from you on how to make the tools even better!