Advancing 112G SI/PI Techniques (Knowledge) by Catching the Advanced Signal Integrity Forum

If you missed the Signal Integrity Journal Advanced Signal Integrity Forum, broadcast September 13, 2023, you can still catch it on demand. The forum comprises four one-hour talks with Q&A and highlights the latest 112G SI/PI technical advances by Cadence and industry-leading Cadence customers Micron and Apex.

Keynote: S + I = $ - How to Succeed at a Career in Signal Integrity

Presenter: Donald Telian, Signal Integrity Consultant

This unique talk blends data-rate-dependent SI design guidance with the three keys to succeeding at a career in signal integrity, revealing the answers are less intuitive and more fun than you thought.

A Systematic Methodology for DDR5 SI Analysis

Presenter: Dirgha Khatri, Principal Signal Integrity Engineer, Micron, and Pankaj Ahirwar, Principal Signal Integrity Engineer, Micron

The storage and computing demands of cutting-edge solutions, such as AI/ML, automotive, enterprise, and storage applications, are driving Micron DRAM products to operate at unprecedented speed limits. This presentation discusses how Micron utilizes Cadence system simulation tools to perform accurate SI analysis, which is essential for minimizing failures and guaranteeing reliable performance. It will also cover SI challenges encountered at different stages of system-level analysis.

Signal Integrity Signoff Methodology for a Multi-Chiplet Package

Presenter: Suresh Subramaniam, Systems/Packaging Lead, Apex, and Abhiram Chandrashekar, System Analysis Engineer, Apex

Apex Semiconductor has developed an industry-first chiplet-based SmartNIC platform composed of a CXL I/O hub and two 8-core RISC-V processors in conjunction with ecosystem partners DreamBig, Ventana Microsystems, and BlueCheetah. This talk presents a signal integrity signoff methodology for the three high-speed interfaces (including 112G) on this platform using the Cadence Sigrity tool suite.

Seamless Design and Analysis for 112G System Interfaces

Presenter: Yun Chase, Solutions Architect, Cadence

This overview presents workflows using Cadence design and analysis tools that address challenges and reduce engineering time in optimizing 112G high-speed interconnect and equalization setup to meet bit-error rate, COM, and other signal integrity requirements. The presentation features a multi-board case study where modeling the full 112G channel, including the connector, is discussed.

Click the below image and learn on-demand now!

Team Sigrity