Lack of design-chain collaboration prevents SiP to go mainstream

A few years back, I was considering that the lack of an integrated design solution (tool flow) was the reason that SiP design was an "expert engineering" process -- and why it was not adopted more widely despite its benefits over SoC integration for a broad range of applications and markets.

However, since the initial release of our SiP solution (http://www.cadence.com/products/sip/index.aspx) a while back, and after having worked with several customers in the adoption of the provided complete design solution, I found that design chain was the key limitation today.

Collaboration across the design chain must be facilitated because, in order to effectively design a SiP, a complex design chain of system, SoC, circuit, package, and board designers will be involved.

Traditionally, these designers have worked independently and designs have been created, simulated, implemented, and verified separately using different tools, methods, and flows, often without a single ‘system’ level circuit simulation view of the entire design.

Major issues exist when it comes to manufacturing. The backend implementation is typically done at the package foundry as it was 20 years back in the ASIC world. Things like a PDK (Process Design Kit) as in the IC world including for example DRC rules to enable the physical verification of the package layout do not exist.