Get email delivery of the Cadence blog featured here
This is the
first in a series of blogs focused on how you can make your design cycle
predictable and shorter for PCB designs that are increasing in complexity. PCB
designers have to deal with increased complexities while design teams are dispersed geographically, and the time to finish the design is continuing to shrink.
Some of these PCB design trends are being fueled by the desire of consumers for
smaller, cheaper, faster and more functional electronic products. This trend is
not just limited to the high-end consumer electronics market segment.
One of the major contributors to the
complexities on PCBs is the increase in the number of constraints on a net. A
few years ago the metric used was number of nets that are constrained in a
design. Each net at that time had a limited number of constraints. Now, with
the increased use of standards based interfaces such as PCI Express, DDR2/3,
and Serial ATA, the number of constraints on a net are also increasing.
Additionally there are intra-group and inter-group constraints. For instance
all the signals in a byte lane on a DDRx interface need to be matched within 50 mils
of each other, and the byte lanes must be within 800 mils of each other.
increase in the number of constraints and complexities, you cannot just rely on
a system that captures and stores constraints, like a fancy properties editor.
What you need is a system that not only helps you create design intent
(connectivity and constraints together), but also makes it easy to implement
your PCB designs easily using these constraints. It should highlight any errors
created during PCB implementation through netlist changes, from interactive etch
edit to manufacturing prep. Real time feedback on basic constraints like inter- and intra-group constraints is important to avoid unpredictable design
iterations at the tail end of the design flow right before going to manufacturing.
managing Electrical Constraint Sets (ECSets, for short) is easy with the Allegro
PCB Design XL suite. This suite offers PCB designers the
capability to “apply” the topologies specified in the ECSets. Topologies for today’s
standards based interfaces like DDR2, QDR, XAUI often call out for T-Points and
constraints for managing lengths/delays from Driver to the T-point. "Topology
Apply" in the Allegro PCB Design XL suite automatically creates t-points, applies
rules to a group of signals, and monitors adherence during design implementation
of a complex PCB. Topologies in ECSets allow users to specify optional pins to
reuse an ECSet to additional buses with same constraints with additional
receivers on one or more nets in a bus.
To learn more
about how you can use Allegro PCB Design XL suite to Apply Electrical
Constraint Set (Topology Apply) to groups of nets (interfaces/buses) quickly
and then monitor any violations during the design flow, watch this archived
webinar -- Predictable,
Shorter Design Cycles for Dense, Complex PCBs. The webinar uses real design data to show how you
can use this capability in the Allegro PCB Design XL suite to shorten your design
cycle while making it more predictable.
Feel free to comment or ask any
questions about this topic. You can also send email directly to me at email@example.com for a private exchange of
information or queries.