Cadence OrCAD and Allegro 22.1 HotFix 003 Is Now Available

The HotFix 003 (QIR2) update for OrCAD® and Allegro® 22.1 is now available at Cadence Downloads. This blog post contains important links for accessing this release and introduces some of the main changes made and the new features that you can look forward to.

    OrCAD/Allegro 22.1 (SPB221)

Here is a representative list of the changes and enhancements across products with brief overviews.

Allegro PCB Editor and Allegro Package Designer Plus

• Performance enhancements continue in this release to speed up design time. Some of the significant changes in this release include faster cline editing in designs with 100,000 or more attributes, increase in stream-out speed, faster generation of Gerber/Artwork, and so on. 
• Three new 3DX DRCs for checking physical violations between models, the PCB, and rigid-flex objects are introduced.
• Creation and editing of zones in Allegro® PCB Editor has been enhanced for Rigid-Flex designs that require different stack-ups. You can now create nested zones and edit zone boundaries outside the shape-edit application mode.
• Allegro® Package Designer Plus now includes Sigrity technology-driven high-speed analysis and checking environment with four products.
• Degassing holes are now preserved when shapes are converted from static to dynamic; you can also control void spacing during degassing.
• Daisy Chain, a prototype Allegro Package Designer Plus feature, enables you to create daisy chain patterns of net assignments and routes for components or specified sets of pins. Instead of using only the pin numbers, you can now create customized net names by adding suffixes or prefixes.

Allegro Pulse

• New checks are introduced for Pulse clusters. These checks include minimum hardware requirements, CPU usage, RAM consumption, and free disk space. An alert is also issued if the Pulse cluster is deployed on a Windows machine or a virtual machine.
• Server modes are introduced. Pulse can be run in the EDM mode for Design Entry HDL setups or as a test or staging server.
• The Pulse cluster now has auto-recovery capabilities. It attempts to restart unresponsive services up to three times.

Allegro System Capture

• For DE-HDL projects, in addition to the schematic, you can now import the complete physical folder or a specific layout file. The last used board file in the DE-HDL design is set as the current board and is immediately available in the new Allegro® System Capture project.
• In system-level designs, logical boards now support an option to exclude a block from all functionality and reports. When enabled, all lower-level circuity is ignored from navigation, the Port/Pin Assignment dialog box, and system connectivity reports.
• Starting from this release, the pin text is also swapped along with the pin number. This is helpful for users who rely on pin text more than pin numbers. This feature is available when you set the ALLOW_PINTEXT_SWAP directive.
• When checking the design integrity, you can use negative temperatures and locate inductors that have multiple pins connected to the same physical net.
• In addition to the parts in the base design, Part Manager now flags modified or stale parts in design variants.
• In the single-user Allegro System Capture environment, you can now perform an advanced search with filters and free-text search. You can also control default settings for column widths, column visibility, column order, and locked chiplets globally or for specific projects.
• New dialog boxes and controls are available for Pulse-related operations in single and multi-user environments. You can check details of Pulse operations, Pulse health status, and configure settings for shared designs, such as the number of local backups, when to create versions, option to lock the complete design, and many more.

Topology Workbench

• Starting this release, Optimality Intelligence System Explorer is supported in the Topology Explorer workflow.
• In the SLA workflow, Optimality Intelligence System Explorer now supports PAM4 interfaces.
• The PBA workflow now supports full bus simulation for address and data buses in a single run.
• A new option, Pole Zero Transfer Function, has been added to the Continuous Time Eq (CTE) module of AMI Builder Wizard to support the use of poles and zeros of the transfer function while modeling CTE.

These were some of the top changes that are available in the HotFix 003 update of the 22.1 release of Cadence OrCAD and Allegro.

For more information on the new features and enhancements made across products, see What’s New in Release 22.1.

We’ll soon be back with more in-depth blog posts on the new features and enhancements made across products, so watch this space.

In case you have questions or feedback, send them to pcbbloggers@cadence.com.

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Allegro Release Team