Online Panel: Chiplets and 3D Heterogenous Integration

Microwave Journal and Signal Integrity Journal recently spearheaded an online panel discussing chiplets and heterogenous integration. Ken Willis, Cadence's senior application engineering group director, multiphysics system analysis, provided his take on the challenges of advanced packaging technologies such as chiplets and 3D heterogenous integration, including integration, stacking, signal integrity, and thermal concerns. He and fellow panel members Chandra Gupta of Remtec and Florian Herrault of PsudolithIC, Inc. examined the simulation, testing, and performance advantages of various approaches to overcoming these challenges.

Key discussion points included the drivers pushing the industry toward chiplet architectures and 3D heterogeneous integration, the most significant electrical challenges to chiplet design, strategies to ensure stable power delivery while minimizing noise, IR drop, and coupling between dies, and how multiphysics co-simulation, including electrical, thermal, and mechanical effects, is helping predict real-world performance.

Ken commented that the biggest change in the design process between traditional semiconductor design and the needs of today's heterogenous integration requirements is the need for system planning to determine how functions are going to be partitioned and placed across multiple physical fabrics.

Through silicon vias (TSVs) and hybrid bonding are some of the many different choices that place the burden on the front-end engineering team to make feasibility and tradeoff choices between these different options to decide on the best implementation path. (Note: Cadence Integrity 3D-IC Platform, Virtuoso Studio, Allegro X APD, Celsius Thermal Solver, Clarity 3D Solver, and Sigrity PowerDC optimize TSV and hybrid bonding designs for HPC and AI applications, ensuring scalability and reliability.)

Ken also noted that power delivery networks (PDNs) for heterogenous systems have become quite complicated and the designer now needs to look beyond the chip design to the entire system from beginning to end because all the different PDN pieces need to be modeled and then simulated together. The challenge is that there are now multiple layouts databases, and solvers and one environment is needed that can take it all the data in and simulate it accurately. (Note: Sigrity X Platform, Clarity 3D Solver, Celsius Thermal Solver, Integrity 3D-IC Platform, Virtuoso Studio, and Allegro X APD provide tools for high-power computing (HPC), AI, and 5G applications that help ensure robust SI/PI in multi-die systems, enabling efficient power delivery and high-speed data transfer.)

Multiphysics co-simulation and how the various effects are modeled together was also discussed. Ken ppointed out that IR drop analysis is now being done across multiple fabrics and it is becoming increasingly important to do that in the context of thermal effects because the heat impacts the IR drop of the PDN. Cadence offers an electro-thermal co-simulation solution to obtain a temperature aware IR drop.

Also becoming more prevalent in the heterogeneous integration space is electromechanical analysis. When designers begin stacking die and have multiple dissimilar materials, thermal stress and warpage become an unknown that must be addressed. (Note: Cadence's multiphysics solutions, including Integrity 3D-IC Platform, Sigrity X Platform, and Clarity 3D Solver are being used to predict and optimize real-world performance in advanced 3D-IC designs, reducing risk and improving reliability.)

View the entire recorded event on demand, including all the discussion points and comments from all the panelists. View our Accelerating Chiplet Integration in heterogenous IC Package Designs on-demand webinar to learn more about a novel new methodology that enables early and iterative optimization of IC package designs. This approach eliminates the need to wait for complete designs or spend excessive time preparing simulations. By integrating in-design analysis and optimization with Cadence's scalable multiphysics analysis engines, IC package engineers can accelerate design cycles and efficiently improve complex package designs.