BoardSurfers: Optimizing Designs with PCB Editor-Topology Workbench Flow

When it comes to system integration, PCB designers need to collaborate with the signal analysis or integrity team to run pre-route or post-route analysis and modify constraints, floorplan, or topology based on the results. Allegro PCB Editor and Sigrity Topology Workbench applications provide seamless integration that helps designers save repeated iterations and time.

PCB Editor is a design solution that integrates PCB tools for creating projects, managing libraries, capturing schematics, packaging, placing and routing components, and producing manufacturing output.

Topology Workbench is an advanced SPICE-based time domain and frequency domain simulation and analysis environment that enables you to explore, identify, and solve the adverse analog effects of high-speed digital systems. You can use Topology Workbench to go from performing simple SI and PI exploration to analyzing the most advanced serial link interfaces.

Let’s start with pre-route SI analysis.

Pre-Route SI Analysis

This analysis is done after preliminary placement and before routing. It is a useful analysis from a time-to-market standpoint.

In pre-route SI analysis, you look for the following:

• How placement affects critical delays and reflections in the design
• How net scheduling affects delays and reflections
• The need for terminators on nets in the design
• An early evaluation of the power distribution system

Here is the basic flow of the analysis. After successfully placing components on board in Allegro PCB Editor, you must add device and interconnect models. In Allegro PCB Editor, you can procure or create device models to suit your design requirements. You can add IBIS, SPICE, HSPICE, Spectre, and IML models.

Once the model assignment is completed, specify constraints using Constraint Manager in Allegro PCB Editor. Inside the Constraint Manager Electrical worksheet, you can use the popup commands to export the topology for a selected net to the Topology Workbench. This establishes an interface between the two applications and enables you to simulate the nets in the Topology Workbench. Based on the simulation results, you can edit, modify, set, or unset the constraints and update them directly into the Constraint Manager.

This flow works for multiple electrical constraints, including Net Scheduling, Impedance matching, and Relative Propagation delays.

Post-Layout Routed Interconnect Analysis

Once the results and analysis from the first stage (pre-route analysis) are available, you perform floorplanning, placement, and routing. To run SI analysis in the time and frequency domains, you can export the topology of the required net in the Topology Workbench as described for the first stage. Once the analysis is complete, based on the analysis results, you can change other important parameters such as Stub Length, Impedance, and Length Matching (delay tune).

Once done, click Update Constraint Manager in the Topology Workbench workflow panel to write the modified constraint values back to the design database (Constraint Manager).

If models have not already been assigned to the PCB Editor, you can assign IBIS models in the Topology Workbench as well. You can perform model assignments for various design blocks in the Topology Workbench. You can also assign models using the AMM (Analysis Model Manager) environment, which supports almost all industry-standard component models for simulation.

For more details on using AMM in Topology Workbench for component model assignment, refer to the following:

• How to Import SPICE Circuit Models (*.sp, *.CKT, *.mod, *.txt) Using AMM in Topology Workbench (cadence.com)
• How to assign an IBIS model to a Controller/Memory using AMM in Topology Workbench (cadence.com)

Topology Workbench uses IBIS models and allows both behavioral and transistor-level I/O models for the devices used in the topology. It adds specific extensions, including keywords, to these IBIS model files and automates the connection of the IBIS files with other components in the system.

Topology Workbench utilizes various simulation engines to perform detailed design-oriented analysis for pre-routed and post-routed, high-speed parallel bus (DDRx/LPDDRx) systems and serial link (SerDes) systems.

You can further add probes in Allegro PCB Editor and take them to the Topology Workbench to see and analyze the output of your simulations at desired probe points.

DesignLink: Multi-Board Analysis

In addition to pre- and post-route analysis, where you can transfer information like time-critical constraints, length matching, net scheduling, and topology using the interface between the two tools, you can also use the DesignLink: Multi-Board Analysis feature. This feature allows multiple board and package layout files to be linked logically and electrically. For example, a DesignLink connection between the board and the memory module will be created, enabling the co-simulation of both boards as if they were one design.

You can set up a detailed timing analysis from the ASIC components on the main board to the memory devices on the DIMM modules from die to die. DesignLink is also integrated with the Constraint Manager system, allowing full system-level constraints to be implemented across multiple boards for timing and relative propagation delay management of buses and other nets.

Following is an example of the output waveform for a DesignLink board:

To know more about this design flow, see the System Integration: Allegro PCB Editor-Sigrity Topology Workbench Flow RAK by Cadence Application Engineers Mahima Goel and Marthanapalli Shiva Shankar on the Cadence Support portal.

In this RAK, PCB Editor is used to create the netlist and perform pre-layout analysis and constraint management. This RAK takes you through several design stages commonly followed in the industry – pre-layout stage, post-layout stage, and the multi-board concept. Through topology generation and simulations, you can explore the solution space and create a set of constraints. These constraints are easily transferred to the Topology Workbench, where you can also define the constraints and perform transient simulations. Later, you can transfer the updated constraints back to the PCB Editor environment. In the post-layout simulation stage, the actual extraction engines create electrical models from the layout and run both time-domain and frequency-domain simulations, displaying the results.

If you find the post helpful and want to explore the Allegro PCB Editor platform, enroll in the online training courses available on the Cadence Support portal. You can become Cadence Certified after the completion of a course.                        

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