The HotFix 028 (QIR4, indicated as 2022 in the application splash screens) update for OrCAD® and Allegro® is now available at Cadence Downloads. This blog post contains important links for accessing this update and introduces some of the main changes made and new features that you can look forward to.
OrCAD/Allegro 17.4 (SPB174)
Here is a representative list of changes and enhancements across products with brief overviews.
DesignTrue DFM continues to evolve and in this release, checks are added for the same net vias. This is an improvement from the generic via pad and hole checks that were available until now. You can also add region-based DFA rules to PCB designs, such as default component spacing DFA rules for the entire design, or one or more regions in the design.
An automatic method is provided for replacing existing differential pair transition vias with differential pair structures by window selection on canvas. This change from the earlier method of cut-splice routing is a time-saver. You now place the structure then route up the connections. Also included is an option to convert a differential pair structure to standalone differential pair transition vias when major rework is required.
In Allegro® Package Designer Plus, package design integrity checks are now introduced that can identify potential opens or shorts for zero-drill diameter padstacks. With the Silicon Layout option, you can now be sure that the power nets are delivering the required power and ground net coverage with the Power Delivery Rail and Via Generator feature. A new Allegro Package Designer Plus Viewer is also available.
The backdrill solution is enhanced to provide a dynamic mode showing backdrill results in real-time while maintaining appropriate backdrill clearance and depth as updates are made.
Multi-drill and keepout enhancements are made to Padstack Editor. Multi-drill patterns now include Polar or Custom arrangements that give you the flexibility of adding different hole patterns, so you no longer need separate via arrangements inside the pad boundary. In this release, you can assign flash symbols with up to two shapes as a padstack keepout, and even allow some objects inside the padstack keepout.
Hole-to-hole checks can now use separate values for thru via holes, blind or buried holes, micro via holes, and pin holes in both the Spacing and Same Net Spacing domains.
Allegro Constraint Compiler (ACC) has many Object table enhancements for selecting objects beyond pins and nets. Flexibility for optional nets has been introduced that allows the compiler to continue even when a net does not exist. For DDR Memory interfaces, it is now easier to assign the second differential pair strobe for each byte lane with the enhanced Byte Lane Diff Pair Calculator.
3D Canvas includes many user experience enhancements, such as transparency controls for symbols and models, Z-origin visualization, and silkscreen layer representation. This release introduces the splitting of planes across different stackups and zones to make 3D Canvas as realistic as possible.
A new workflow called Interconnect Model Extraction (IME) has been introduced. This simplified and automated model extraction utilizes Sigrity PowerSI® or Clarity 3D Solver licenses to extract highly accurate S-Parameter models.
Starting with this release, Allegro System Capture is integrated with PSpice® A/D to provide a functional circuit simulation environment. You can now run all types of analysis, such as transient, AC and DC Sweep, Bias point, and Parametric Sweep from Allegro System Capture. PSpice Advanced Analysis, MATLAB visualization, and MATLAB functions are also available.
It is no longer mandatory to set the scope of power and ground symbols to global. You can now change the scope of these symbols to local when designing a schematic. New options to hide pages, reorder blocks, and create hierarchical variants are also available with site-level directives.
When working with remote Allegro® Pulse servers and managed libraries, Unified Search shows larger images of symbols and footprints making it easier to view intricate model details. Searching is now classification aware.
In the library authoring environment, you can now create asymmetrical schematic symbols. You can even create a new symbol without having to create a part first, that is, you no longer need to create parts and symbols together.
You can also create non-electrical symbols that are helpful in documenting information on the schematic, such as page borders, title blocks, and table of content symbols. Creating power and port symbols is also now supported.
Some changes are made in toolbars and menu commands to provide a consistent UI when authoring schematics, symbols, library parts, and board files.
The overarching topology creation and editing environment that includes Topology Explorer (TopXplorer), Sigrity SystemSI, and SystemPI are now named Topology Workbench.
In complex topologies, such as CAN bus for automotive applications, you can use the Cable modeler block and build twisted cable SPICE W-element models for simulation.
The Windows GCC compiler is now included in the AMI Builder and you can compile AMI models on the Windows platform for the SLA and PBA workflows.
Memory blocks in a topology are no longer limited to the same IBIS or SPICE models. You can now assign different IBIS or SPICE models to memory blocks in a topology.
Many performance enhancements are added. The run time for S-parameter simulation in SPEEDEM is now reduced. The algorithm used in solving sparse SPICE circuits is enhanced by a new multi-threading architecture and matrix partition solver.
You can use expressions instead of values for the various parameters, such as Initial Condition (IC), Parasitic Resistive Element, Temperature Coefficient, and Voltage or Current Coefficient values when creating PSpice components with Modeling Application.
Adding a center tap to both the primary and secondary windings of a transformer is now possible. Until now you could define center taps only for primary or secondary windings.
Advanced debugging information for simulation runs is available. This debugging information includes simulation settings, accepted time points, count of rejected steps, and worst signals with failed iteration values for convergence failures.
The debugging information is available as CSV and Excel reports.
These are some of the top changes that are available in the QIR4 release of Cadence® OrCAD® and Allegro 17.4-2019. For more information on the new features and enhancements made across products, see What’s New in Release 17.4-2019 HotFix 028.
Watch this YouTube video Cadence OrCAD and Allegro: What’s New in HotFix 028 for more details on these features. We’ll soon be back with more in-depth blog posts on new features and enhancements made across products, so watch this space.
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Allegro Release Team