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With thousands of components connected across a multi-layered board, anticipating the complexity of your layout design at the logic design stage can be quite a challenge. For example, how to ensure that the logical design you are trying to create functions correctly in the layout as well? There might be a possibility of a short circuit if you draw wires that are too close, or there could be other issues that might lead to a circuit failure. So, what is required is a mechanism that can help you catch and fix violations at the logic design stage, ensuring that your designs do not fail in the field.
To ensure the logical and physical integrity of a design, you can define and run a comprehensive set of Design Rule Checks (DRC) within Allegro® System Capture. Performing DRCs helps you verify design-related constraints and avoid problems in manufacturing circuit boards. Even if your design is simple, you must run the DRCs to ensure correct electrical and logical functionality and manufacturability.
Allegro System Capture lets you set up the rules for design auditing and run the checks to ensure that the components are ready for the successful manufacturing of circuit boards. Running the electrical checks generates a schematic audit report that helps you verify and fix the violations. Keep reading to know how you can set up and run DRCs in Allegro System Capture.
Setting up DRCs is a quick and easy process within Allegro System Capture.
The following table lists the various categories of rules and the violations they check for:
The rule names under each category are predefined and cannot be changed. You can, however, modify the report type to prioritize the severity of a rule. The report type can be set to values Fatal, Error, Warning, Information, or Do not run.
Allegro System Capture offers a gamut of pre-defined DRCs to verify design violations. To run the standard DRCs, from the main menu, choose Design Integrity – Audit Schematic.
Allegro System Capture audits the schematic by running the DRCs and generates a Schematic Audit Report, which is displayed in a new tab. This report is divided into the following three sections:
Let’s take an example to understand this. A violation value unavailable on a component R/L/C is reported on running the checks. To resolve this issue, right-click the violation message and select Highlight. This command redirects you to the schematic page where the resistor is placed with no value assigned. You can specify a value for the resistor to fix the violation. On running Design Integrity – Audit Schematic again, note the screen text, No violations data.
You can also waive the DRCs in case you want to hide any violations flagged in the report. The violations can be reinstated in the report later using the Unwaive command from the shortcut menu.
The use of DRCs at the logic design stage is a highly recommended practice for layout preparation. DRCs help you review the design data that is used for manufacturing PCBs. By performing these physical checks in Allegro System Capture, you can identify and fix errors with the design components and connectivity and pass the data for the successful manufacturing of circuit boards.
In a nutshell, DRCs help you:
To learn in detail about Design Rule Checks (DRCs), watch How to Run DRCs in the Allegro System Capture tool. training byte on the Cadence Support portal. Click the training byte link now or visit Cadence Support and search for this training byte under Video Library.
If you find the post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design: Allegro System Capture v17.4-2019QIR4 (Online)
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