Power-Aware SI DDR4 Simulation: You Have a Choice!

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO) has been a hot topic for decades in signal integrity (SI) circles (see figure to the right).  Some claim only a SPICE simulation using transistor-level models can provide the accuracy required for memory interfaces such as DDR4 that drive multiple signals in unison on both the address and data bus.  And even with a SPICE simulator and transistor-level models, interconnect models need to provide the details that show the interaction between signal, power, and ground.  Some believe models such as this can only be extracted from a physical test bench using a vector network analyzer (VNA).  However, if you have a PCB from which to perform physical model extraction, then you are late in the product development cycle and most design teams would like to perform these simulations early in the design cycle to help optimize the power delivery network, signal routing, and memory controller selection.  

The Cadence®⁾ Sigrity team has been evangelizing a power-aware signal-integrity methodology for some time.  But now, we’ve got something new to talk about.  Before going any further, however, you may want to take a few minutes to review the flow we had in place for some time by reading through our whitepaper: Addressing the “Power-Aware” Challenges of Memory Interface Designs.

This whitepaper reviews the well understood (but harder to execute) flow for power-aware SI that extracts interconnect models on a system, such as package model, PCB model, and connector model, then cascades them with IBIS (5.0+) device models to form a system for time domain simulation. Sigrity SystemSI^(TM) has been supporting such flow for several years.It uses Sigrity extraction tools to extract PCB and/or Package models from the physical layout, assign the model to a block, connect the signal, power, and ground signals of each block, and runtime domain simulation using a SPICE-like simulator to generate waveforms for post-processing. The non-ideal power supply effect is simulated by including power nets during interconnect model extraction, connecting the proper power supply pins from the driving buffer to the receiving buffer, and using power-aware IBIS models in time domain simulation.

The flow works fine when all the models are extracted properly and the return current path with the correct power ground pins are identified and connected, provided that the time domain simulator can handle the large complex system level simulation.

Unfortunately, the sheer size of the interconnect models (i.e. S-parameters) can cause long simulation times.  The board and package S-parameters can have hundreds of ports when signal and power nets are extracted together for a bus design. Since S-parameter models do not have information at DC, time domain simulations can encounter convergence problems when an S-parameter model is not well behaved in the lower frequency range.

When design teams do get results from this type of simulation, they are then challenged to debug design problems because once the package and board model are extracted, any physical information in the layout is lost. Therefore, if SI engineers want to correct problems revealed by the time domain simulation of the system, they have to go back to the layout, make a change, and extract the model again. Obviously, this is not convenient for “what-if” analysis.

Can we have a power-aware simulation flow that avoids using model extraction and reduces the chance of convergence failure? The answer is YES. Sigrity SystemSI and SPEED2000 now work together to make this available to SI engineers. In the new workflow, instead of extracting a model from a layout, SystemSI has a new block that is directly linked to a board or package layout. Once the flow is enabled, direct FDTD simulation using the hybrid solver is performed in SPEED2000 in the background (see figure below). When the simulation completes, results come back to SystemSI for post-processing and measurements. To a user, the interface and setup process is the same as using the flow with extracted models.

The key difference here is that the new flow does not use a SPICE-like simulator, but instead, a FDTD method with a hybrid solver, for time domain simulation.

This flow enables design teams to perform “what-if” analysis by directly accessing the package or board layout, reduces interconnect model complexity, and makes simulation convergence issues a thing of the past.

So, you may be wondering if the methodology discussed in our whitepaper is now obsolete.  Well, not so fast.  If you are late in the design cycle and have some of those VNA extracted models, that is a perfect time to use the block-based interconnect model approach. But, if you are still in design validation stage, have access to the layout, and expect to make modifications, the direct FDTD simulation method would be the better choice.

For more information about this FDTD based power-aware simulation please take a look at our Sigrity Tech Tip video: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters).