Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0

The peripheral component interconnect express (PCIe) high-speed interface has become the standard interface for computer expansion cards for graphics, solid-state drives, etc. due to its high bandwidth combined with manageable component costs. The latest version 6.0 is on the way, with the PCI Special Interest Group (PCI-SIG) having published the final specs in January 2022. And it promises even faster data rates, which raises new challenges for design engineers as the popular interface standard moves to pulse-amplitude modulation-4 (PAM4) signaling for the first time.

Here, Cadence offers a complete signal integrity (SI) and power integrity (PI)  design and analysis workflow that significantly reduces the time to signoff for PCIe 6.0 devices. Watch this on-demand webinar to learn how design teams utilize the Sigrity X platform for early what-if analysis scenarios at the system level to realize optimized solutions.