Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6 APD and SiP Layout

Perhaps the most time-consuming aspect to designing the package substrate for a large, high pin count flip-chip comes in the form of package routing. Escaping from underneath the flip-chip die itself, routing through multiple substrate layers, and finally connecting to the assigned BGA balls might easily account for 75% or more of the time spent on the substrate layout. Add the optimization of the routing to meet timing and SI constraints, and that percentage climbs even higher.

It is with this in mind that Cadence has developed an advanced package auto-router optional add-on to both Allegro Package Designer (APD) and SiP Layout products. Read on to learn more about this tool.

Advanced Package Router Option for IC Packaging Tools

This router, currently targeted specifically at dense, high pin count flip-chip substrates, excels at efficiently routing across multiple layers. It offers multiple strategies for via placement, prioritization between overall routing completion or route quality, and advanced options like length matching. Shown below is the user interface for the router – as simple to use as it is powerful.

To further enhance your experience, this new router is tightly integrated into the etch editing application mode. By accessing the router from within the app mode, you can quickly pre-select specific nets or groups of nets to route, saving you time analyzing the overall routing potential of the die within the context of a selected package substrate size and cross-section.

Cadence customers can view a short video that covers the key functions of the APR tool, including the user interface and routing. 

To learn more about how this new router can help you meet your time to market deadlines, or to provide feedback on the tool, speak with your Cadence sales representative.

 Jeff Gallagher