Register Now: Tackling the Complexity of Next-Generation IC Packaging

Today’s IC packaging solutions continue to grow in complexity, posing several challenges. Because of the high costs of moving to next-generation silicon nodes and the need to integrate additional high-density memories for AI-based applications, designers of system-level IC packages need to better understand the impacts between integrated silicon or component blocks. Cadence’s in-design analysis (IDA) solutions integrate signal integrity, power integrity (SI/PI), and thermal validation directly into its PCB layout platforms, enabling engineers to obtain a real-time snapshot of the effects of placement and proximity on electrical performance early in the design process. This innovative approach uncovers problems that can be corrected before the final validation stage, cutting up to 50% of design respins.

Register Now

Learn how Cadence is addressing these challenges and view real use-case scenarios in a webinar on August 28 at 11:00 am presented by the Northeast Microelectronic Coalition (NEMC).  Mark your calendars and register here to attend this free webinar to gain valuable technical insight into system-level design and analysis of next-generation IC packaging using Cadence tools.