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By Brad Griffin
Don’t miss this insightful half-day on-demand webinar event available to view through Signal Integrity Journal and featuring a breadth of industry expert presentations:
Al Neves, chief technologist officer at Wild River Technology LLC, gives a keynote focused on a systematic method of benchmarking EDA performance and ensuring consistent simulation to measurement results in today’s accelerating convergence of tightened signal integrity requirements.
Kundan Chand, power integrity engineer, Meta Platforms, presents a power delivery network (PDN) measurement methodology and correlation exercise, compares the simulation results to measurement, and discusses the results.
Electromagnetic (EM) simulation of large chip-package designs using the Cadence Clarity 3D Solver is discussed by Nicholas Swart, principal CAD engineer at Analog Devices. Detailed results of Clarity’s simulation performance obtained on ADI’s compute farm are presented, where ADI has been able to easily simulate a large, complex system-on-chip (SOC) laminate in approximately 15 hours with modest per-machine memory consumption.
Lastly, Kristoffer Skytte, senior principal application engineer at Cadence, presents a case study sharing experience and best practices for achieving measurement-to-simulation correlation based on the Wild River CMP 50 IEEE P370 compliant test fixture where lab measurements were taken from DC to 50GHz. Topics such as material property identification, correlation challenges, influence of connector models, and manufacturing tolerance/variation are covered.
For additional details and to register to view one or all of the presentations, visit the SIJ site here.