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By Dr. John Dunn
Modern electrical system design for 5G wireless systems and connected devices for automotive, radar, and semiconductor technologies is constantly being pushed to operate at higher frequencies.
With this comes a corresponding increase in design complexity that necessitates densely packed components and more sophisticated package requirements. As such, EM simulation has become an essential and critical part of the design and verification process of analog/high-performance silicon chips.
Silicon is the pervasive technology choice for high-speed digital and RFICs. Traditionally, designers have relied on parasitic extraction tools to model the passive layout on the chip, such as the various nets connecting the devices. However, these tools have accuracy limitations when used for layout components with electrically large areas (relative to frequency wavelength) and highly complex geometry features.
This recently published white paper overviews the complications presented to EM simulators when analyzing silicon layout and showcases specifically how the EMX Planar 3D Solver readily addresses them.
Click here to continue to learn more about silicon IC in-design electromagnetic analysis/modeling.