Shorter, Predictable Design Cycles (SPDC) – Ensuring Critical Signals Have a Return Path

This is third in the series of blog posts about making your design cycles predictable and shorter for dense PCBs that have highly constrained high-speed interfaces such as DDR2, DDR3, SATA II/III, and USB 3.0. The first post talked about using ECSets to ensure that the interfaces are designed correctly, and that the system provides feedback with all the changes that come along the way. Changes can come from, but are not limited to, multiple netlists/ECOs from the hardware designer. In the Far East, the frequency of such changes while the PCB layout is in progress is far higher than in North America, Europe or Japan.  However, 3-4 ECOs in a day are not unheard of in North America.

The second post focused on dynamic phase control for high-speed differential pairs. Dynamic phase control provides feedback to the users as the differential pair is being routed. Feedback during initial etch creation is important on dense, highly constrained PCBs in order to avoid rework at the tail end of the cycle -- which makes completion of the design unpredictable.

With increasing pin counts and decreasing pin pitches on BGAs, the ground/power planes are becoming worse than Swiss cheese. There isn’t enough copper on these planes to provide a return path for the break-out trace segments. This can create a problem with the critical high-speed signals not having an appropriate return path if you are not careful.

Allegro PCB Design XL allows users to easily detect segments of signals that are over voids (created by clearance pads on pins or vias) in ground/power planes.  Once you detect these signals through a simple utility (Segments Over Void), you can apply another utility (Spread Segments) to adjust trace segments between pins of BGAs (instead of having to manually edit the trace segments), assuming you have enough room to do so.

The first screen shot below shows how Allegro PCB can identify segments that can potentially cause return path issues. The second one shows the Spread Between Voids capability.

Figure 1 -- Segments Over Void: Identifies cline segments crossing over antipads and a split plane gap.

Figure 2 -- Spread Between Voids: Before spread (left), after spread (right)

To learn more about these capabilities, watch this archived webinar – Predictable, Shorter Design Cycles for Dense, Complex PCBs. This webinar shows how Allegro PCB Design can shorten your design cycles and make them more predictable.

Feel free to comment on this or contact me directly via email – shah@cadence.com

Hemant Shah