Streamline Your PCB Design Flow with In-Design and Post-Route Power Integrity Analysis

Designing an optimized power supply and a PCB without board-level SI/PI problems on time requires a tight collaboration between the design, layout, and PI engineers through an integrated design platform.

A team-oriented design flow will empower the design and layout designers to perform basic Power Integrity (PI)  analysis early in the design cycle without overburdening the PI engineers, resulting in a quicker time to market and a cost-optimized final design.

The traditional roles in the PCB design flow

Generally, the three main roles in the PCB design flow are all responsible for ensuring the Power Integrity of a PCB:

1. The design engineer role initializes the process by generating the build of materials (BOM) and the circuits’ schematics and begins the cost feasibility analysis of the PCB design. The problem of AC power delivery and noise margin falls into the domain of the design engineer role.
2. The layout engineer role generally controls the metal shapes, vias, component/trace placement, and spacing; this role also handles DC power delivery and current density constraints.
3. The PI engineer role is intricately involved through the entire design process and is relied upon to perform detailed, full-board, frequency domain analysis to eliminate complex PI issues while optimizing cost versus performance.

A design engineer can face obstacles early in the design while making the initial choice of decoupling capacitors (decaps). Many device vendors do not specify decap selection on their datasheets, which leaves the design engineers with a complex task of interpreting specifications to assign decaps to all the unique components.

In the layout stage, an inexperienced layout engineer can be overwhelmed by the sheer number of planes and traces in a PDN; issues can pop up before signoff, thereby lengthening the design cycle.

Typically, the PI expert is utilized continuously throughout this design cycle for basic PI analysis, such as DC IR drop and decoupling capacitor (decap) placement. This frequently leads to a back-and-forth between the team members for even simple tasks, leading to a rather disjointed team with poor utilization of the PI expert’s time. This “over the wall” approach is time-consuming and cumbersome.

So what can be done to solve contemporary PI design issues?

Many of the current issues found in the PI design cycle can be solved with a design platform that caters to the individual members of the PI design team. The pre-layout stage would be simplified for design engineers with an upfront analysis to determine the ideal decap selection. Additionally, design engineers can better produce a foundation that can be built upon by the layout and PI engineers later in the design cycle by preparing the design for in-design analysis. For instance, this can be done by providing decap placement guidance for layout engineers down-the-line, drastically simplifying the layout process where thousands of decaps can be assigned to a single net.

During the layout stage, the PCB designers can perform in-design DC analysis such as IR drop analysis; thus, unburdening both the layout engineer and the PI expert from tedious, error-prone tasks. PI experts can also use the prep work initialized by the design engineers to rapidly shift to the design analysis phase as opposed to spending time doing the prep work.

The design cycle utilizes an iterative approach to generate a robust PCB. Any changes that the PI engineer makes must be (simply) communicated back within the design platform such that the layout engineer can rapidly locate and verify the changes made to fix the specific design issue. In this process, designs would have fewer iterations, schedules would be more predictable, and initial prototype designs would work the first time.

The Cadence Allegro PCB Design environment along with Cadence Sigrity power integrity tools enable a smoother design cycle through tools catered to a team-oriented design flow. The PowerTree Utility, for instance, graphically displays connectivity from the VRM to all integrated circuit (IC) devices (including decaps) (Figure 1). Through this utility, hardware engineers and PCB designers can share a common setup file to perform simulations and PDN analysis on planes and routed power nets for each voltage. A design engineer can perform simulation of the tree with only component data, identifying the potential issues with device selection well before these issues would be flagged using the typical layout-based PI analysis. The layout engineer can also use this utility for guidance on the placement and routing of the PDN. Later in the design cycle, the PI expert can use the same PowerTree setup file to automate the PDN simulation setup, saving critical time in the design cycle.

Figure 1: The PowerTree graphically displays source/sink definition, discrete values, model names, net names, decap values, and target impedance constraints of the PDN while also automating simple analysis for hardware engineers and layout engineers to utilize later in the design cycle.

Power integrity constraint sets (PI Csets) generate a uniform interface for design-intent information by saving all component-level PI information. This includes component names, physical placement guidance, and the quantity of each component per power rail while also automating the instantiation of components and updating the BOM. The PI Csets creation is made easy by the tool’s Power Feasibility Editor ― the platform with which datasheet decap selection and physical placement guidance can be entered. This editor can set up high-level specifications to generate target impedance profiles thereby simplifying the early design process of decap selection while also generating placement constraints for layout engineers.

Layout engineer-driven DC analysis simplifying the PI expert’s job

Typically, PI experts are relied upon for IR drop analysis due to its complexity ― calculating IR drop manually is nearly impossible with the plated through-holes and vias that generate complex shapes, moreover, DC IR drop is a non-linear analysis that is temperature-dependent.

However, the Cadence Sigrity PowerDC analysis engine provides linear electrical/thermal co-simulation to successfully address the non-linear electro-thermal effects on the PCB. Due to the straightforward simulation of IR drop and temperature rise, the layout engineer can be empowered to perform this analysis early in the design cycle without necessarily relying upon the PI expert. PCB designers can create initial PDN constraints using automated IPC calculations to establish targets in their design without guidelines from the PI expert. In Figure 2, the IR drop workflow demo shows how a PCB designer starts off loading the PowerTree provided by the PI expert to ultimately visualize the IR drop directly on the Allegro canvas. This empowers the layout team to rapidly pinpoint and resolve PI issues without burdening the PI expert. This type of dynamic DC analysis early in the design stage minimizes the design rework that inevitably occurs upon the PI expert’s feedback.

Figure 2: (3a) IR drop workflow begins by uploading the PowerTree and analyzed signals are color-coded based upon the amount of IR drop estimated. This is all readily visualized within the Allegro canvas. (3b) Further review reveals vias choking power from the source to the sink. (3c) Removing/moving these vias passes the requirements.

Design engineer guidance regarding placement of decoupling capacitors

The integration of the constraint set in the design environment with the layout environment yields a visual representation of decap placement ― a critical aspect of PDN design that is often tedious in layout. The visual guidance shown in Figure 3 can be invaluable in the initial layout stage of the PDN, mitigating time-consuming LVS errors down the line. In essence, layout designers can independently edit and reanalyze without impacting the PI expert’s workspace. Ultimately, the PI expert can backannotate PDN changes to the layout, which, in turn, is conveyed back to the design engineer with an automated update of the schematic, BOM, and the constraint sets. This integration in software dramatically smooths out the process of conveying and updating design changes while empowering the design engineer and layout engineer to grasp the AC/DC effects of said changes from the PI expert, potentially accelerating the process of gaining PI expertise as a team.

Figure 3: Constraint-based guidance for decap placement dynamically occurs in the layout based upon location of the cursor with respect to the local availability of metal shapes on power and ground layers.

Conclusion

Within the design cycle, there is a need for a tight feedback loop between the layout engineer and the SI/PI engineers to iteratively improve the design. In some cases, this either leads to an overlap in expertise with a tightly connected design team (a relationship that takes years to develop) or, often, a disjointed team in which the layout engineer may be working in the dark without design guidelines.

Design tools can be an invaluable asset in tightening the collaboration between the PI experts and PCB designers. Allegro PCB Design Editor and Sigrity Aurora offers a seamlessly integrated platform between AC/DC analysis and layout so that the PCB design teams can more rapidly approach signoff with a reliable, cost-effective product.

We put together this fun little video for you to imagine two different design teams within your company.  One using traditional “best in class” tools and the other using a fully integrated Cadence flow.  If you are a design engineer, PCB designer, power integrity engineer, or design team manager, we think you may see some familiar challenges.  More importantly, you will see solutions using the team-based PCB PI solution available now from Cadence.

Team Sigrity