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To successfully develop and maintain designs, you need some way to track changes to a schematic and layout to determine which version of a logic design was loaded into your PCB.
In an Allegro® Pulse-managed environment, you can easily synchronize schematics and layouts by linking them for netlist exchange. When linked, Pulse maintains a link between the version of a schematic that drove the netlist of a PCB and the version of the PCB that was back annotated to the schematic.
So, how do you link them? All you need to do is add the Ready for Layout tag when committing a logical design that you shared with layout designers. When layout designers link their layout with the shared schematic by importing the logic netlist, linking is complete. PCB designers can now easily trace which version of the schematic netlist the board is using and whether there are any schematic updates.
Similarly, layout designers can add the Ready for Schematic tag when committing a shared layout, and schematic designers are notified in Allegro® System Capture that a newer version of the layout is available for syncing.
Schematic designers can then reimport the netlist to synchronize the schematic with the layout.
Likewise, an Allegro System Capture designer can also establish a link between the schematic and the layout by importing a PCB layout from Pulse and selecting the required compatible design from the list of designs. After the design is saved, Pulse imports the layout netlist and links the schematic with the selected layout. If, for some reason, you need a previous layout version, select it from the Version Control dialog box.
How do you check for compatibility of linked designs? Each commit with the Ready for Schematic or Ready for Layout tag changes the design netlist. For example, after a netlist is imported into a layout from a schematic committed with the Ready for Layout tag, each subsequent version of the layout that is created is considered compatible with that version of the schematic. This compatibility continues until a new version of the schematic is published with the Ready for Layout tag and is imported into the PCB design.
If you want more information on how to delink a schematic and layout, check the product documentation. Also see Schematic and Layout Linking in Allegro Pulse, System Capture, and PCB Editor.
Keep watching this space for more information on schematic and layout linking. For example, after linking, you can choose layouts from Pulse instead of a local machine when publishing derived data to a PLM system. Or read about managing the layout and schematic linking with third-party board design partners.
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This ASCENT series is for the Allegro System Capture product suite that includes applications and features, such as Allegro Pulse, Unified Search, Part Manager, Constraints Manager, Live BOM, Team Design, and System Reliability to name a few.
In this series of posts, we discover what Allegro System Capture is and how you can use it for creating parts, libraries, and designs, reusing established IP, all the way to creating layout files while managing design costs, time to market, standards compliance, and providing access to non-EDA support functions.
So, whether you are a single designer wearing multiple hats or a large enterprise, Allegro System Capture has something for you. Stay tuned as we share tips and tricks to smooth your ascent!