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The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence®. In addition to providing insight into the useful features and enhancements in this area, this series aims to broadcast the views of different bloggers and experts, who share their knowledge and experience on all things related to System Analysis.
When you are under pressure to complete the chip-package co-analysis signoff, you will need flexibility in the way you define the port groups. With the help of Enable PLOC Optimization option in SigrityTM XtractIMTM Technology, you can optimize Pin Location (PLOC) grouping. The support for PLOC Grouping Optimization has been a catalyst in improving the run time and memory in VoltusTM IC Power Integrity Solution for large packages. Using PLOC file optimization, you can achieve faster signoff with chip-package co-analysis. You can load a PLOC file generated by Voltus IC Power Integrity Solution and use per-pin RL analysis for packages to output a better PLOC grouping file in XtractIM. This optimized port grouping file has pins of similar inductance and resistance, and minimal pin-to-pin resistance. By just adjusting the threshold, you can quickly re-create the PLOC file without running the simulation. The PLOC grouping optimization accelerates the time required for signoff and allows you to run simulations efficiently on modestly equipped computers, thus letting you run chip-package simulation of large packages and also improve the simulation capacity. To utilize the Enable PLOC Optimization option, follow these steps:
Let’s begin by loading the test case file in XtractIM. You can load the OPT_PLOC_01.ximx file from <Sigrity2021_install_path>\doc\XtractIM_Tutorial\tutorial_examples.
Now, Select Simulation Setup –> Setup for Power / Ground Analysis. This is where you achieve the first step of PLOC optimization. Select the DiePad-to-BGA DC Resistance and Enable PLOC optimization options. Choose the power and ground nets from the Nets to Be Assessed list. Now, run the simulation.
After the simulation is complete, you can proceed to the next step of achieving PLOC optimization in the View/Export Results category. Under Per Pin Properties, select Setup for PLOC Optimization. Then in the PLOC Optimization Setup window, select the Assess input PLOC Groups option. Now, set the following options:
Now, load the optimized PLOC file in Load MCP header/PLOC file. After clicking Match Package, the MCP Auto Connection window displays. You can easily match the pins on the SPD layout database with the pins on the PLOC file. To do so, select the two pins, Left Pin1 and Left Pin2 from the left circuit node. Similarly, select the two pins, Right Pin1 and Right Pin2 from the right circuit node. Then, click Match.
You can view the Pin Mapping Report by clicking View Pin Mapping in the MCP Auto Connection window.
If you are satisfied with the pin mapping, click OK.
After saving the changes made in the PLOC Optimization Setup window, select PLOC File after Optimization under Per Pin Properties to view the new PLOC grouping file.
See how easy it was to optimize a PLOC file! To learn how to create a PLOC file and connect the die to the package in a detailed step-by-step manner, refer to the video mentioned in the Related Resources.
XtractIM User Guide
Pin-Based Model Extraction Using PLOC File in Sigrity XtractIM
Hope you found this information useful and will try out the Enable PLOC Optimization option to optimize a PLOC file.
Stay with us as we continue to explore what’s new in the world of Cadence Sigrity and Systems Analysis. For information about the most recent enhancements, check the Sigrity and Systems Analysis 2021.1 What's New. Happy reading!
For more information on Cadence Sigrity and Systems Analysis products and services, visit www.cadence.com.
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