Verifying multi-technology chips-in-a-SiP, fact or fiction?

With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?"

If you have ever pondered this challenge, or have tried and failed, or tried and suceeded you may be interested in this article in ChipDesign Magazine.

Have a read. I have some thoughts on this but would like to hear yours first. Let me know what you think.