What's Good About Using Allegro TimingVision and IPC-2581 to Reduce Design Costs? Check Out These Expert Insights Videos!

This week, you can view a couple of videos where customers describe how they used Cadence's Allegro TimingVision technology to achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems of their designs and the IPC-2581 design data format and Allegro PCB Editor tools to eliminate surprises at the final stages of PCB design.

Cavium

Routing boards with high-speed interfaces had been a time-consuming, manual process at Cavium. To alleviate scheduling pressures without sacrificing quality of their multi-layer boards, the San Jose, CA, semiconductor company automated the process with the Allegro TimingVision environment. In this three-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems. After watching the video, learn more about the Allegro TimingVision environment.

Tejas Networks

In this short video, Amba Prasad, product architect, R&D, at Tejas Networks, explains how the IPC-2581 design data format and Cadence Allegro tools eliminate surprises at the final stages of PCB design. These technologies are helping Tejas Networks deliver high-quality products faster than their competitors.

I hope you enjoy watching these!
Jerry "GenPart" Grzenia