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This week, you can view a couple of videos where customers describe how they used the Sigrity and Cadence SiP Digital Layout products to simulate, verify, and reduce the size and costs of their designs.
Ericsson Meets DDR and PCIe Specs While Avoiding CrosstalkIn this Expert Insights video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified their design to meet DDR and PCI Express (PCIe) specs while avoiding crosstalk. They were able to simulate and verify using Cadence's Sigrity solution with the IBIS/AMI virtual reference design for interface compliance signoff, which they found to be easy to set up and easy to test, while saving them time and money. After watching this video, learn more about Cadence Sigrity SI/PI solutions.
Reducing Cost, Size of PCBs with Embedded Technologies and Cadence Layout ToolsDialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications. After watching this video, learn more about Cadence SiP Digital Layout.
I hope you enjoy watching these!
Jerry "GenPart" Grzenia