What's Good About OrCAD Capture’s Signal Integrity Flow? The Secret's in the 16.6 Release!

With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment.

Capturing constraints early in design cycle is important for the following reasons:

• Quality challenges as the design cycle for any PCB product is shrinking day by day
• As the edge rates are shrinking, it is necessary to constrain the critical signals up-front to avoid signal integrity issues
• As a result,engineers are forced to move some of the tasks early in the design cycle, which might cause more iterations if taken at the final stage of board designing
• Enabling pre-route constraints cuts down the design iterations, enabling designers to deliver shorter design cycles

Read on for more details…

Here is an overview of the Capture – SI flow:

SI Model Management (associate models to schematic instances)
• Setting up SI Model Libraries
• Auto Generate Models for discrete components
• Assign Models to Parts and Pins

Explore Signals (associating explore signals and managing ECSets on schematic XNets)
• Export XNET to Signal Explorer (SigXP)
• Assigning topologies to schematic XNets
• Validate topologies on schematic XNets

Export/Import ECSets (exporting/importing ECSet assignments from/to the schematic)
• Export ECSets from the schematic to SI Expert
• Import ECSets to the schematic from SI Expert
• Export ECSets to physical layout
• Import ECSet changes from physical layout

Export/Import with Allegro PCB Editor (taking the ECSet to/from Allegro Layout)
• Netlisting to Allegro
• Backannotating from Allegro


There are two methodologies for managing constraints:

Please share your experiences using this new 16.6 capability.

Jerry “GenPart” Grzenia