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With the SPB16.2 release, a few new FPGA enhancements have been added.
In recent years, the design of FPGA and Printed Circuit Boards (PCBs) has become increasingly parallelized as opposed to the traditional sequential model.
Earlier, Capture CIS was only capable of generating a single section part when PCB designer uses the .pad or pin files to generate a part. In the 16.2 version, Generate Part has been enhanced such that PCB designer can generate a part based on the information like IO Banks/IO Standards/power pins in one section, pins visibility in a very easy and efficient manner.
There are several occasions throughout the design process where pinout changes may happen in the schematic tool and must then be propagated to the FPGA user constraint file (UCF). For instance, the board design may have started before the FPGA internal logic. Therefore, pins may have been added, removed, renamed, or relocated. The schematic engineer may also discover improperly assigned pins or that the system specifications have changed requiring more, fewer, or different I/O properties. The Xilinx ISE user constraint file (UCF) must be kept in sync with the board I/O to avoid a system malfunction. You can make a swapped pin symbol and create a .ucf file during the Export FPGA.
As always, I look forward to your suggestions about these new enhancements.