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With the SPB16.2 release, a few new FPGA enhancements have been added.
In recent years, the design of FPGA and Printed Circuit Boards (PCBs) has become increasingly parallelized as opposed to the traditional sequential model.
Earlier, Capture CIS was only capable of generating a single section part when PCB designer uses the .pad or pin files to generate a part. In the 16.2 version, Generate Part has been enhanced such that PCB designer can generate a part based on the information like IO Banks/IO Standards/power pins in one section, pins visibility in a very easy and efficient manner.
There are several occasions throughout the design process where pinout changes may happen in the schematic tool and must then be propagated to the FPGA user constraint file (UCF). For instance, the board design may have started before the FPGA internal logic. Therefore, pins may have been added, removed, renamed, or relocated. The schematic engineer may also discover improperly assigned pins or that the system specifications have changed requiring more, fewer, or different I/O properties. The Xilinx ISE user constraint file (UCF) must be kept in sync with the board I/O to avoid a system malfunction. You can make a swapped pin symbol and create a .ucf file during the Export FPGA.
As always, I look forward to your suggestions about these new enhancements.
Hi Vid Shaw -
I'd recommend you contact our Support team for this specific question. They will assist you in the details.
I am using ORCAD 16.6 to export Xilinx FPGA pin config file which can be used by Vivado/ISE. I tried right click on FPGA symbol and use "Export FPGA", choose UCF or CVS, get "pin number" and "net name" information.
However, I got no info about pin's direction, io standard... where should I set these attribute for pins in ORCAD, so I can get a more complete .ucf or cvs file which can be imported into Xilinx ISE or Vivado. Thanks, and Merry Christmas!
Following is excerpt from cvs file, you can see, only Pin Number and Signal Name is exported, other attributes is empty.
Pin Number, Signal Name, Direction, IO Standard, Drive (mA), Slew Rate, Termination, IOB Delay, Diff Type, Diff Pair, Swap Group
(1).Following is excerpt from cvs file, you can see, only Pin Number and Signal Name is exported, other attributes is empty.
(2).Following is excerpt from ucf file, also, only Pin Number and Signal Name are exported.
NET "DDR_BF_RST_N" LOC = "H12";
NET "DDR_BF_DQ4" LOC = "G10";
NET "DDR_BF_DQ2" LOC = "G9";
Hi, The OrCAD 16.2 Demo Software can be downloaded from now. Lool at www.cadence.com/.../downloads.aspx. Best regards, Ole
Hi Jim! Glad to see you're still using the Cadence tools! For those who may not know - Jim is a long time Allegro customer who has provided numerous product suggestions with some becoming new features in the product. He's an expert with out products. I'll send you a private Email Jim so we can "catch-up". Jerry
Jerry it's good to see your still around and doing well ? It's Jim from USR. Later.
Hi ten vn Q227. There's no "demo" software per se. You can obtain an evaluation copy of the OrCad software by contacting your Cadence Sales Representative in your geography. Please contact him or her for details.
I would like to download the OrCAD 16.2 Demo Software. Please help. Thank you