What's Good About The SPB16.3 Release? It's Here - Download It now!

15 Dec 2009 • 2 minute read

The SPB16.3 release is now available (actually, it was available last week from the Cadence software downloads site at - http://downloads.cadence.com/).

Where has the year gone! It seems like only yesterday I was blogging about all the cool new SPB16.2 features - and now the SPB16.3 release will add additional improvements and efficiencies to your design process.

Over the next several weeks, I'll be writing about key new features available in this SPB16.3 release. You've seen my previous posts about the high level benefits and the SPB16.3 Virtual Conference, but now I'll focus on specific details. I'd like to hear which features that you've been waiting to see are the most important and useful for your design requirements and which features you'd like us to tune in future releases.

Here are a few highlights:

Allegro PCB Editor

Placement Replication / Placement Fine Tuning
Create/Disband groups in Pre-selection mode
Polygon Selection Window
Customizable Datatips
Resize Line Width and Gap of Differential Pairs
3D Viewer
Flip Design
Etch Editing Enhancements
Exclusive Microvia Stacking DRC Checks
Via List DRC Checks
Design For Manufacturing Updates
IDX Support
New variables for SPB16.3
Allegro PCB Router - Use Via Region
Allegro PCB Router - Diff Pair Improvements
Allegro PCB Router - BB Via Clearance
Allegro PCB Router - Stacked Via Support
Allegro PCB Router - ARK option alignment
Allegro PCB Router - Highlight / Unhighlight bbvias
Allegro Constraint Manager - Match Via DRC
Allegro Constraint Manager - Max Via DRC
Allegro Constraint Manager - Differential Impedance in Constraint Manager
Allegro Constraint Manager - Differential Pair Renaming
Allegro Constraint Manager - Dynamic Phase Control for Differential Pairs
Allegro Constraint Manager - Online Formula Calculation
Allegro Global Route Environment - Bundle Edit Functionality
Allegro Global Route Environment - Expanded Rake Functionality
Allegro Global Route Environment - Plan Status and Router Status
RF PCB - Asymmetrical Clearance
RF PCB - Allegro Discrete Library to Agilent ADS Translator
many many more ...

Allegro PCB SI & RF SiP

SigXp UI Enhancements
Simplifying the Use of Third-Party SI Models
Model Editor
DML Path Setting
Case Management
Modeling of Metal Surface Roughness
Signal Quality Screening
PCB PI Discontinuity Modeling
RF SiP - Alignment of Library Manager Use Model with Custom IC Use Model
RF SiP - Model Import and Assignment without Packaging
RF SiP - IC Packaging: Simulate IC in Context of Package
RF SiP - Enhancements in DIE Use Flow

Allegro Package Design & System In Package

ADRC Integration with CM
Super Smooth
Wire Bond Updates

Allegro Design Entry HDL

Improved Font Support
Alignment and Distribution
Anchor Point wire stretch
PCB Librarian - Font Support
Constraint Manager - SI Model Library Management
Constraint Manager - Diff Pair Renaming
Constraint Manager - New Properties

Allegro System Architect

Schematic Generation Improvements
Export Packagable Schematics
Differential Pair Renaming
Performance Improvements
Signal Integrity Model Changes

Allegro Design Workbench

Library Flow - Improvements
Library Flow - Part / Model Status Changes
Library Flow - Deleting Models
Library Flow - Mechanical Parts
Design Flow - Component Browser
Design Flow - LRM
Design Flow - Mechanical Parts
Administration - Flow Manager
Administration - Configuration Manager

Allegro Design Entry CIS

Auto wiring
Browsing for Power Pins
Changing color, look and feel of Wire/Bus and Hierarchal blocks
Intersheet References
Locking Objects on Board & Schematics
Placing OLE objects
CIS Relational Table Enhancements
3D Footprint Viewer

Allegro AMS Simulator

Probe Enhancements
Cursor Enhancements
New Design Templates
Highlighting in circuit and out files
Changing Font Properties
Exporting a Comma Separated (CSV) file
Faster dat file import and export
New Models in SPB16.3

I'm looking forward to your feedback!

Jerry "GenPart" Grzenia