What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting the new FPGA System Planner (FSP) product from the Cadence Silicon Package Board (SPB) division at the recent CDNLive! EMEA event.

You can watch Hemant from the event:

Available in two forms - Allegro FPGA System Planner and OrCAD FPGA System Planner - this new technology works in the respective Allegro/OrCAD front-to-back flows.

Some of the differentiators of the new FPGA System Planner compared to what's available on the market today are:

• FPGA System Planner (FSP) automates the pin assignments. For large pin count FPGAs (300, 500, 1000 pins or more), this is a very laborious process which is greatly streamlined with FSP.
• FPGA System Planner considers the PCB routing architecture when assigning and thus optimizing the pin selections.
• High level (system level) component connectivity is considered for multiple FPGAs and other components when synthesizing the optimal pin assignments.

One of the customers using this technology had 4 FPGAs on the PCB and were able to reduce their design cycle by 4-6 weeks.

Another customer used FPGAs to do ASIC prototyping. They constructed a design containing 48 FPGAs on 5 separate PCBs using FSP. This took only HALF the time compared to a design with 19 FPGAs on a single PCB with a manual approach - which amounts to about an 80% - 90% design cycle reduction.

Even with just a single FPGA on a single PCB, working with FSP in the OrCAD front-to-back flow, customers can realize benefits due to eliminating the manual approaches (wrong pins on the clock, wrong voltage pins assigned, etc.) which lead to errors caught in the lab after the PCB is prototyped.

As always, I welcome your comments and suggestions about the new FPGA System Planner product.

Jerry "GenPart" Grzenia