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The Sigrity Aurora online course provides the essential training required to start working with Sigrity Aurora. The course covers the design flow from simulating a pre-routed parallel bus to constraining the PCB routing based on the simulation results. Constraints are created in Topology Workbench and Allegro® Constraint Manager to verify that the post-routed parallel bus meets the design requirements. The post-route analysis continues with the Sigrity Aurora workflows for analyzing impedance, crosstalk, and the voltage drop across the power delivery system. We upgrade this course regularly to be in sync with the latest changes in the product.
Some of the main topics in the Sigrity Aurora online course that might interest you are discussed here.
IBIS models are used to model the drivers and receivers of a parallel bus. In the design flow, you will assign IBIS models to the FPGA memory controller and the memory components in the design.
You will also create a SPICE model for a DIMM memory connector pin to increase the accuracy of your pre-route simulation and analysis.
Based on the parameters of your PCB cross-section and trace widths, lossy trace models can be easily generated in Sigrity Aurora to better model the transmission lines in the parallel bus simulation.
In Module 5 of the course, you will learn how to use Trace Editor to create parameterized RLGC models to model the transmission lines of the parallel bus. The models are based on the PCB cross-section and use the length of the transmission line as a variable parameter to sweep the lengths for solution space analysis.
Sweep simulations allow you to vary the lengths of the traces used on the parallel bus, so you can find the minimum and maximum connection lengths that enable you to meet the design constraints.
Module 6 of the course takes you through the solution space analysis of the parallel bus so you can measure the setup and hold times between the strobes and the data bits. You will also display the waveform as an eye diagram to measure eye openings, widths, and heights.
Data from the sweep simulations is used to create constraint sets that drive the placement and routing of the PCB. Any routing that does not adhere to the created constraints is flagged with a design rule error.
In the course, you will import the constraints created in Topology Workbench to Allegro Constraint Manager and see how these constraints can optimize the placement of the parts on your PCB. You will then work with a routed design and use the Allegro® PCB Editor interactive routing commands to resolve the connections in the design that do not meet the constraints set in Allegro Constraint Manager.
Sigrity Aurora provides many in-design analysis workflows that you can use to analyze the routed design. The workflows enable quick analysis of transmission line impedance and coupled crosstalk through the design. The workflows also include the analysis of the voltage drop across the power planes and shapes in the design.
In the course, you will use the different workflows to analyze the routing of your parallel bus. In Module 9, you will explore the IR Drop workflow to analyze the voltage drop across the power plane that supplies power to the memory controller and memory DIIM.
To learn about this course in detail, watch the Sigrity Aurora Training video and enroll for the Sigrity Aurora course on the Cadence Support portal.
Click the training byte link or visit Cadence Support and search for this training byte under Video Library.
If you find this post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design:
Sigrity Aurora v22.1QIR1 (Online)
You might also be interested in the training Learning Map that guides you through recommended course flows as well as tool experience and knowledge-level training modules. To find information on how to get an account on the Cadence Learning and Support portal, see here.
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