Get email delivery of the Cadence blog featured here
So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!!
Now I kinda understand that this could be true for chips that go into leadframe packages, but...for example, lets take a complex wireless radio chip design that end up in routable substrate package (BGA/LGA), now the design team surely needs to consider the package at some stage?
Do these circuits designers really ignore package effects? Do they never communicate with the package designer? not even to send them a basic footprint and pinout of the chip?
I'm hoping that some of you do care, that you need to "interface" with the package design team, and if so, how is it done today, what works, what doesn't and what makes you want to rip your hair out? So come on, let me know, let eveyone know!