IC Packagers: Coming Soon to a Blog Near You…

What is new in the Cadence® SiP Layout and APD tools?  Is there reason to get excited to pick up the most recent HotFix of 17.2 (or update from release 16.6 to 17.2 at all)? The answer is a most emphatic YES. Join us as we start our journey, exploring all that is new to the tools lately (and revisiting a few of the classics, of course!). We'll try to cover all the topics that might interest you as we go, looking at a new area every week.

As a preview of what is coming, over the few months, we’ll be covering:

• Daisy chain test vehicle design for your ICs and packages
• Thermal expansion considerations and design tools when packaging
• Adding two-sided die components to your layouts
• Optimal design of copper pillar components to ensure problem-free, reliable substrates
• Importing parts from Excel spreadsheets and exporting changes to them

If any of that sounds interesting to you, come back tomorrow when we begin our journey with a discussion of how to make daisy chain test packages in fewer than 5 minutes with 17.2 SiP technology. From there, we’ll cover the gamut of new features recently added (or significantly enhanced) in the tools. We suggest you click the SUBSCRIBE button now so you don't miss anything.

And, should you have a topic you want to learn more about – or if you want to tell fellow designers about a feature that led to significant time savings and yield improvements for your team – be sure to let us know. Our team is revved up and ready to share. Saving you time to market is just one of the targets we take aim at each and every day!