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The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do not use a front-end schematic. Even if you have a schematic, you may find yourself making logic swaps in the layout where the additional context of the routing paths is critical to decision making.
Helpfully, the Allegro Package Designer Plus toolbox, unlike many ECAD layout tools, provides a full complement of logic editing features. You can create and delete nets, assign to individual pins, or propagate from one component interface to another. This flexibility is core to the nature of the package as a redistribution (and protective!) substrate for the smaller die.
Today, we’ll cover some of the more common scenarios. These apply whether you have a single flip-chip on an interposer, a set of stacked memory die on a BGA, or a full complement of devices arrayed in a system in package.
The Logic - Auto Assign Net command has been in the Allegro Packaging tools for many years. I suspect many of you reading are familiar with it. But, no discussion of connectivity in a package is complete without it.
If you are starting a new package design, the seed netlist will often come from the dies being packaged. Once they are read into the layout, a BGA of the appropriate size and pin count is added. Then, you need a way to get the die’s signals out to the balls. Unless you have a pre-defined netlist for the BGA, Auto Assign is a great way to do this.
There are two algorithms available for assignment. The nearest match will attempt to minimize the total ratsnest length for all the connections while also creating the fewest possible crossings in the flight lines. Constraint driven will look at more detailed requirements for propagation delay, differential pair memberships, and similar factors. It will satisfy as many of these as possible.
When you have picked the appropriate algorithm and identified some basic requirements such as the creation of nets for unassigned pins in the source and whether to treat any existing BGA ball assignments as immutable, selecting the to/from components (or sets of pins) and a press of the assign button will give you a reasonable seeding for the net mappings of the package.
Now, it is important that you bring in all die components before doing this, so the tool has the contextual information to make intelligent decisions. If you have a set of stacked die with shared signals internal to the package itself, you don’t want BGA balls being assigned for them!
If auto-assignment isn’t an option for you, maybe you need to start routing and see where it takes you. Later, when you are happy with how things look, you can commit the assignments to the BGA.
To do this, make use of the assignment capabilities built into the interactive routing tools first. Shown below, turn on the auto-assign unused pins option if you want to assign to the BGA as you work. In this case, when you arrive at your destination and click, the BGA ball will be assigned to the die pin’s net to complete the connection.
This can be highly useful and save you a step later. BUT, as soon as you have assigned the BGA ball in this method, you have locked it and the auto-assign option in the router will not change it in the future. You will need to manually unassign the pin if you want to remap it (or use one of the logic swap commands).
To leave your options fully open, then, you can instead leave this unchecked. The BGA ball will not be assigned. Instead, you will get a spacing DRC violation between the end of the routing and the pin. This marker need not deter you, however! It can drive another logic menu command – Derive Assignment – to lock in the assignments when you are ready.
Shown above, the main option to be concerned with is stretch traces. When this is on, if your early routing just ended “on” the ball pad, not necessarily at the exact connect point, derive assignment will adjust things for ideal connections. This can ensure clean fillet shapes among other things.
Derive assignment serves a second purpose in that it can use DRCs to resolve and make assignments to other objects (vias, shapes, bond fingers), not only pins. Use this to have the system assess routing and shapes to assign voltage nets to plane shape areas based on what they tie to.
Finally, what happens when you get ECO changes to one component (normally the die) and need to push those out to the BGA? The 17.4 QIR1 release (hotfix 007) introduced a new logic management feature: push connectivity. To enable this, enable the icp_push_connectivity option in your user preferences and restart the tool:
You will find the new command in the Logic menu, alongside the other commands we’re talking about (right below Derive Assignment, in fact!). This command is designed, specifically, to enable you to take a component whose net assignments have been updated and selectively push those new nets out to items that share physical connections to the pins.
This is different from the derive assignment tool, which only resolves connectivity to dummy net objects and is DRC driven. No DRC violations drive the push tool. Just the physical routing paths in the layout itself. Thus, the interface’s options are very simple – there’s only one option! – as we can see below:
When the advance selection option is on after you select the set of pins from which to push connectivity, you will see a form listing all the nets and their pins, you can whittle things down to. Whether you want to push only the signal nets, or only the nets from specific pins on those nets, you can tailor the selections here (hint: You will notice this same interface in the auto-assign net tool!). This isn’t in conflict with the find by query interface. You are free to use either! For a one-time action, the advanced selection filter may be faster with its more focused tree view of the selected data. But, if you already have queries saved for other uses, grab one of those! The most efficient way for you is going to be the BEST way.
Once you have exactly the items you want to be propagated, start the process. The database will find any connections to those nets and update the assignments to any pins, vias, and shapes it encounters. Unlike the derive assignment tool above, push connectivity will reassign nets to those elements currently on different real nets, not just dummy net objects.
For your own confirmation, after the assignment changes are complete, a report is presented showing everything that was changed:
Remember: we can’t cover everything in a short blog entry like this! I haven’t specifically talked about co-design die components and the flow with those today. With any co-design die component (which thus understands the first level of cell hierarchy in the die to be able to validate proposed package assignment changes against the impact to the I/O macro placement inside the die), APD Plus will prevent you from making edits that cannot be made to the IC layout. This will help minimize your back-and-forth with the die design team as you optimize the bump pattern.
Check out the many other commands across the File – Import and Logic menus, plus the Symbol Edit application mode, for the best solution for your specific need. Should you not find it, reach out to your customer service team expert for help!