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When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong?
The most common reasons I see for this include:
A simple mistake during import of a die text file,
The lack of DIESTACK layers in the design when bringing in a wire bond die, meaning it automatically got changed to a flip-chip due to no legal layers for a wire bond part,
Default components coming from the front-end schematic through forward annotation, then when placing the component forgetting to identify the attachment type in the options panel, or
Adding a two-sided die and being unsure which side are the front pins of the die and how they connect to the substrate.
Now that the component is placed in your design, what is the best way to go about finding the problem and, most important, correcting it? Recent improvements to the SiP use model – as requested by some of you! – make this easier than ever if you’re using a recent hotfix of release 17.2.
Maybe you are in the wire bond edit application mode and can’t add bond wires to any of the die pads – a sure sign that something is amiss. To confirm, or to detect, the problem, leverage the built-in facilities. In this case, rather than the Database Check (since this is not a problem with the database, rather it is an incorrect status of an object) run the Package Design Integrity command in the Tools menu.
This command (which, by the way, your group can add to if you have errors that you know have slipped into your designs) looks for issues that may be incorrect. Many of the rules offer the option to correct the configuration automatically for you, whether it is to align a via with its connecting pin or removing duplicate bond wire guide paths.
The Die Attachment Method and Die Symbol Orientation checks are what we are interested in this time. Run this at any time on your design and receive a report of any die components that are called flip-chips but look like they should be wire bond, or chip-down dies that probably were meant to be chip-up.
Package Design Integrity won’t automatically fix these problems for you. Doing so would involve changing the orientation of the component (and thereby break connections if you added some escape routing to your wire bond die) or changing the layer that it is placed on in the vertical stack up ordering.
Now that you know your die component D1 is incorrectly a chip-down flip-chip, fixing it is a simple matter. All corrections should be made in the die stack editor, which is the environment for establishing all manner of attributes for your dies and their relationships.
See your die’s attach type and orientation by selecting its parent die stack from the pull-down list in the form, or just click on the die in the canvas, which will automatically select the die stack and update the stack’s member list in the grid at the bottom of the form.
Correcting the attachment type, now, is as simple as it can be. Click the pull-down and pick the correct value. If you’re changing a flip-chip to a wire-bond die, the front layer will be updated to the closest legal DIESTACK type layer, so you might want to make any necessary adjustment to that while you’re here.
The same is true for fixing the orientation. Changing between chip up and down will update the mirror geometry status of the symbol at the same time, but it will stretch any connected routing or bond wires for you to keep your design as close to what you intended as possible.
Repeat this process for any additional components that need to be updated. When you’re finished, close the die stack editor, save your design, and continue.
While you have the die stack editor open, if you are changing from flip-chip to wire-bond, take a moment to see if any spacers or adhesive definitions are also missing. While a flip-chip is connected to the substrate with its bumps, a wire-bonded die is connected using adhesive.
Change to the member details view in the die stack editor grid and set the adhesive dielectric material and thickness. This saves you from defining a separate spacer element in your die stack, eliminates the need for a named dielectric layer to hold the spacer, and automatically adjusts the spacer’s size if the die size changes through an ECO request later.