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Leadframe package designs are here to stay, and they are getting more complex with every passing year. New materials and manufacturing processes allow for the inclusion of more active and passive components, while new bonding capabilities stretch the available pin counts.
At the same time, signal, power, and thermal integrity challenges continue to mount. Simple designs, which could previously be done inside of a mechanical CAD tool, now are subject to tighter design rule checks. Running SI analysis and manufacturing checks is now imperative. Enter Cadence SiP Layout, with its host of commands and tool sets designed to help you take your leadframe design from concept to completion faster than ever – and with the verification at all levels to give you peace of mind knowing the final part will work flawlessly in the context of the entire system.
To learn more about what is available in the 16.6 release of Cadence SiP Layout to help you through every stage of leadframe package design, read on.
It’s the first step in any design: getting your components in place. If you have library symbols and device files, you’re all set. But what if you have a GDSII file for your die with simple text labels for the nets, or an Excel spreadsheet pin map of the die pad pattern? Perhaps you have only a DXF file from your substrate provider which defines the lead pattern, paddle, and rings?
Whether your source is a die text file, co-design die abstract, or manufacturing geometry data, SiP Layout has your import and conversion needs covered. With a few commands and clicks of our mouse, you can turn your data into fully-defined components and symbols in your substrate, complete with net assignments, ready for bonding. And, you do all this directly in the SIP substrate design – no need to go into a library part or pad shape editor where you will lose the context of the overall package (important information during any reconstruction of intelligent substrates from geometric data).
Going into all the details of all the various options would take too long. But, here is a handy chart to get you started:
If you have…
Use this command…
CSV text files representing your component
Add -> Standard Die -> Die Text
XDA/DIA co-design die abstract
Add -> Co-Design Die
GDSII or DXF die representation
Add -> Standard Die -> Compose from Geometry
Spreadsheet pin pattern definition
Symbol Edit Application Mode RMB on empty canvas and start a new component.
RMB on the component and add pins by pattern.
Library symbols for off the shelf dies
Logic -> Edit Parts List + Place -> Manually
DXF data of the leads of the leadframe package
Tools -> Convert -> Shape to Padstack
… customization needs for your imported symbol such as a complex place bound outline or pin text placement options
Symbol Edit Application Mode
If you don’t see your particular data input listed above, don’t fear. This isn’t a complete list! Check the File -> Import and Add -> Standard Die menu items, or consult with your Cadence Support representative.
What if you have multiple variant options for this design using different memory quantities or supplies, and want to be sure to bring everything in at once, you ask? Never fear! Cadence SiP Layout will let you identify each individual variant combination and extract individual databases from your master substrate design for verification, analysis, and manufacturing.
Now that you have your components placed and ready to bond, things get even easier. If you haven’t read in your netlist information, however, make sure you do that first so the tool knows which die pads you want to bond to which of the leads on the package.
Import your nets from a spreadsheet, CSV file, schematic, or other source – or define it on-the-fly based on pin names/numbers and optimized assignment from die to package pins. Whatever information is most easily available to you, this step will show you rats nest lines between your dies and out to the leads, and you are ready for bonding.
All your die pads can be bonded to the right leads in a single step using the wire bond application more or the Route -> Wire Bond -> Bond to Leadframe command. As you can see below, set the offset distances from the inside edge of the leads for bond placement (or, if you prefer, you can predefine these offsets in your own wire profile definitions and reference them easily here and automate this step in your flow) and with the click of a button, all your bond wires are created for you.
Now it is time to verify the physical characteristics of the design. You are ready to check your design in 3D to see what things look like (and run some 3D wire-to-wire DRC spacing checks, while you’re at it); run the View -> 3D Model, define your DRC requirements, and generate the view. If you see any issues, you can change wire profiles directly within the viewer, re-run your DRC checks, and push the new profile assignments back into your layout database when things are exactly the way you want them.
Of course, it’s more than just the 3D clearance checks that matter. SiP Layout provides a robust set of assembly rule checks alongside the standard physical, spacing, and electrical rules in the Constraint Manager spreadsheets. Check out the categories below and then look in your Constraint Manager tool to see all the details for yourself and configure your rules.
If you have proprietary rules specific to your manufacturing process, consider the Cadence RAVEL option to define your specific rule checks to be run on the design.
We’re almost there! Now, it’s time to do some analysis of the design and see if everything is within specifications.
The Cadence Sigrity XtractIM tool is a fast, highly capable IC package RLC extraction and assessment tool. With options to generate highly accurate broadband models and support for complex leadframe packages, it benefits from a tight integration with your main SiP Layout design. The Sigrity XtractIM tool seamlessly pulls all the details from your design – 3D wire profile curvatures, solder bump models, and even relative die placement heights in a stack plus the stacks position on the leadframe top or sunken into an open cavity.
If you have multiple variants defined, first use the variant interface under the Manufacture menu to extract the specific variant option to be analyzed. That way, the tool will know what design option you want characterized, checked, and modeled.
Phew. We’ve created the design, added logic, validated that the physical and spacing requirements are met, and made sure our signal, thermal, and power tolerances are in spec. Is it lunchtime, yet? Not even close! It’s time to generate documentation and manufacturing data for this design before grabbing that sandwich.
Whether your needs include bonding diagrams, OLP data, GDSII, DXF, Gerber, or some other data format, you’re almost certain to find an export translator that meets your needs under the File -> Export or Manufacture menu.
But, don’t forget the reports. Manufacturing data isn’t enough on its own. We need documentation! Whether you need a wire bond report, a connectivity report, or a PDF document of the design, output is a breeze. If you should need to highlight some specific areas of the design, use the 3D Viewer’s markup and annotation capabilities to take detailed images with text notations that you can include for reference.
We’ve highlighted only some of the exciting new functional abilities you can find in the 16.6 release to make your leadframe flow the best that it can be. Many more can be found in the tool today, with information and how-to documents available in the self-help resources on the Cadence website.
As these packages continue to evolve and become even more complex, though, there is always room to improve usability, functionality, and capability of the tools. So, if you have an idea for how to make the tool more useful to you, we want to hear from you! Give us a call or send your Cadence support team an email. We’d love to hear from you!