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Recently, we’ve covered some basics about why imported dies default to chip-down flip-chips and even the different types of mirroring. To close on the topic of dies, die stacks, and the interaction of components why may interface together without ever coming into direct contact with the package substrate, I want to take today and explain just how die stacking works in the Allegro environment.
In an IC layout tool or PCB tool, connections are almost exclusively made by routing to the appropriate component pin. It could be a cline/wire/trace or a poured plane that provides the electrical path between two objects, but the fact remains that the path is a combination of horizontal and vertical paths.
Packages, however, add bond wires – which can bend in three dimensions, functioning more like a combination of a via + trace in one object – and direct component-to-component connections, such as a flip-chip mounted onto exposed landing pads of the package substrate or another member of the die stack. All of this occurs in “layers” which are not part of the actual physical cross-section of the package design. This might make things a little more complicated, but (if you ask me) also makes things much more FUN!
Today, we’re not talking about basic flip-chips and wire-bonded dies. More accurately, we can speak about bumps, pillars, direct contact, and bond wires as connection elements between two elements in a stack.
Bumps and pillars achieve a similar net result. You get a solid, stable connection to the next substrate using a small amount of conductive material between passivation exposed metal on the die and the next surface. The connection is much shorter than with a bond wire leading to shorter paths and reduced delay.
The bump, however, is “part of” one of the components. Typically, we consider it part of the die being mounted. The bumps are added to this component’s exposed pads, then heated a second time and connected to the target pads. It’s important to note, then, that from a substrate designer’s perspective, the pad on the chip itself is NOT directly accessible.
That means even if the passivation opening was at the exact same height as a substrate layer, such as for a die placed in a cavity, it is physically impossible to route to the pad on the die itself. You can ONLY route to the connect pad on the substrate itself to which the bump will be mounted.
Because of this, the Allegro tools do not directly model the die pad as an element in the database (unless you’re doing co-design of the die and package together, in which case you can see the internal top-level RDL layers of the chip – but let’s put that aside for today). The tool shows you the contact pad target for the bump or pillar on the layer it is to connect to, as shown above with a flip-chip's bumps routed out on the top conductor layer.
When you pick up and move the die component, the landing pads on the destination layer, along with the body of the die, is what is being moved. If you apply thermal expansion adjustments to the die, the target pads are being adjusted. And, if you change the vertical ordering of the die in the die stack, the result is a change to where the die’s bumps will mount.
When you have two dies together in a stack which interface directly, you have connected, or contact, pads. Using our bump description above, one of the dies is the host and the other the child. The child’s pads are bumped; the host’s exposed connect pads (where the child will be mounted) are exposed metal areas – quite like a bond pad for a wire bond connection. But you best not wire bond to those unless you want a mess during assembly!
In these situations, you will have two pads overlapping on the same layer. Take our example below, which has a flip-chip mounted to contact pads in the center of the host wire bond die.
The size and shape of the connecting pads of the lower die and the landing pads of the upper die don’t need to be the exact same size and shape, but typically they will be. In so doing, you can write an easy check to validate whether there is any difference in the geometries. It’s always nice to have some extra checks looking out for you.
The presence of single-layer pads on both dies on the same layer is crucial. In both cases, the die is an existing object being placed into or mounted onto the substrate. The pads do not connect to anything (directly) on the substrate layers. So, the presence of both pads gives the critical connectivity tracing path between the two components.
Note: Bumps and Wires in the Die Stack Editor graphics Indicate attach type, not actual locations of the items
It is the orientation of the two dies, one chip-up, and the other chip-down, which provide the required context to determine which chip sits above and which below. This is, by the way, why it is important that you bring in your flip-chip dies and mirror them in the package layout design. If you pre-mirror the pad locations and bring it in unmirrored, you are depriving the tool of that piece of critical placement information.
Bond wires are unique. They are about the only connection which spans between two different layers vertically, but with the connect points on the two layers (the start and end of the bond wire) being at different XY locations.
With a bond wire, you can connect a die which sits 500um above the surface – with no piece of it touching the package itself, as it sits on a spacer or another die – down to a bond finger on the substrate top. You can span from a die pad exposed in a cavity up, out of the cavity depression to a finger on the surface. In a pinch, a jumper bond wire may connect to two fingers, two pads, or a combination that exists on the SAME layer (even the same component), going up and over a congested area of routing.
The flexibility of wire connections can offer serious benefits. Imagine a case where you have insufficient room to make a few substrate layer connections. Should you add another layer to the stack-up… at what cost? Would it be cheaper to use a jumper? Are there inter-die connections which could be done with die-to-die bonds instead of substrate routing?
How big would our cell phones be today if, instead of stacked memory dies connected using bond wires, these had to all be placed side-by-side on a single substrate surface?
The three concepts above, combined, allow the Allegro Package Designer Plus suite of tools to accurately understand and model any type of stacked component arrangement. From a simple stack of memory dies bonded to a substrate to a flip-chip die embedded in a cavity with a wire bond die on the enclosed substrate above it.
When you stack components, the key concepts to always be aware of include:
Know where the stack itself rests. Does it sit above the top soldermask layer? Does it mount inside of a cavity, and if so, does the bottom die have bumps which must connect to exposed metal, or is it a wire-bonded die adhered to a dielectric layer?
If you’re stacking things up, make sure your stack is balanced! For situations like staircase stacks, you may need a spacer to level out the area under the upper die to ensure no risk of them falling over during or after assembly.
Allegro models the external interface pads for all components. For wire bond die pads and connect pads, this is the metal ON the die which is exposed through the passivation layer openings. For bumps and pillars, this is the pad to which the bump will be connected during assembly.
Before you consider going to the assembly, look at your design in the 3D Viewer or 3D Canvas. A momentary glance can reveal problems that are difficult to capture from a top-down 2D orientation.
If you’re cognizant of these items, you should have no problem creating even the most complex of stacks. Of course, if you find yourself in trouble, we are always here and happy to help!